verilog手撕代码——找出高位或低位第一个出现1

module find_first
#(
    parameter WIDTH = 6
)(
    input [WIDTH-1:0] req,
    output [WIDTH-1:0] grant
);



genvar i;

if(lsb_first)
    begin:lsb_to_msb
        assign grant[0] = req[0];
        for(i=1;i<WIDTH;i=i+1)begin
            grant[i] = req[i] & ~|grant[i-1:0];
        end    
    end
else if(!lsb_first)
    begin:msb_to_lsb
        assign grant[WIDTH-1] = req[WIDTH-1];
        for(i=WIDTH-2;i>0;i=i-1)begin
            grant[i] = req[i] & ~|grant[WIDTH-1:i+1];
        end
    end

endmodule