近来在校内论坛上看到有位师兄面试海思的时候面试官问了个寻找最高有效位位置的问题,手痒试试看。
题:寻找一16bit无符号数最高bit位的位置
思:主要想法是输出的时延要固定,时延不能跟着位置走。于是想到了二分法,这样的话不论什么数,找到结果的时延都是固定的,且吞吐率还高,每个时钟周期都能吃数,启动间隔为1。
module top_valid(
input clk,
input rst,
input [15:0] d_in,
output reg [3:0] place
);
reg [7:0] d_temp_8;
reg [3:0] d_temp_4;
reg [1:0] d_temp_2;
reg base_place_8,base_place_4,base_place_2;
reg base_place_8_q1,base_place_8_q2;
reg [7:0] d_temp_8_q1,d_temp_8_q2;
reg [3:0] d_temp_4_q1;
reg base_place_4_q1;
wire top_eight;
wire top_four;
wire top_two;
assign top_eight = |d_in[15:8];
assign top_four = |d_temp_8[7:4];
assign top_two = |d_temp_4[3:2];
always @(posedge clk or posedge rst) begin
if(rst == 1'b1) begin
d_temp_8 <= 'd0;
base_place_8 <= 1'b0;
end
else begin
d_temp_8 <= top_eight ? d_in[15:8] : d_in[7:0];
base_place_8 <= top_eight ? 1'b1 : 1'b0;
end
end
always @(posedge clk or posedge rst) begin
if(rst == 1'b1) begin
d_temp_4 <= 'd0;
base_place_4 <= 1'b0;
end
else begin
d_temp_4 <= top_four ? d_temp_8[7:4] : d_temp_8[3:0];
base_place_4 <= top_four ? 1'b1 : 1'b0;
end
end
always @(posedge clk or posedge rst) begin
if(rst == 1'b1) begin
d_temp_2 <= 'd0;
base_place_2 <= 1'b0;
end
else begin
d_temp_2 <= top_two ? d_temp_4[3:2] : d_temp_4[1:0];
base_place_2 <= top_two ? 1'b1 : 1'b0;
end
end
always @(posedge clk or posedge rst) begin
if(rst == 1'b1) begin
base_place_8_q1 <= 'b0;
base_place_8_q2 <= 'b0;
d_temp_8_q1 <= 'b0;
d_temp_8_q2 <= 'b0;
d_temp_4_q1 <= 'b0;
base_place_4_q1 <= 'b0;
end
else begin
base_place_8_q1 <= base_place_8;
base_place_8_q2 <= base_place_8_q1;
d_temp_8_q1 <= d_temp_8;
d_temp_8_q2 <= d_temp_8_q1;
d_temp_4_q1 <= d_temp_4;
base_place_4_q1 <= base_place_4;
end
end
always @(posedge clk or posedge rst) begin
if(rst == 1'b1) begin
place <= 'b0;
end
else begin
place <= (base_place_8_q2 << 3) + (base_place_4_q1 << 2) + (base_place_2 << 1) + d_temp_2[1];
end
end
endmodule
测试结果如下,很完美
大家如果有什么其他想法欢迎在评论区交流。