FPGA入门学习笔记（三）Vivado设计时序逻辑计数器

时序仿真结果

设计文件程序

`timescale 1ns/1ns

module led_flash(
    input Clk,
    input Reset_n,
    output reg Led
);
    reg [25:0]counter;
    // <= 为非阻塞赋值
//  always@(posedge Clk or negedge Reset_n)begin
//        if (!Reset_n)begin
//            counter <= 0;
//            Led <= 0;
//            end
//        else if(counter == 25000000)begin
//            Led <= !Led;
//            counter <= 0;
//            end
//        else
//            counter <= counter +1'd1;
//    end

    always@(posedge Clk or negedge Reset_n)begin
        if (!Reset_n)
            counter <= 0;
        else if(counter == 25000000 - 1)
            counter <= 0;
        else
            counter <= counter +1'd1;
    end
    always@(posedge Clk or negedge Reset_n)begin
        if (!Reset_n)
            Led <= 0;
        else if(counter == 25000000 - 1)
            Led <= !Led;
    end

endmodule

仿真文件程序

`timescale 1ns/1ns


module led_flash_tb();
    
    reg Clk;
    reg Reset_n;
    wire Led;

    led_flash led_flash_test(
        .Clk(Clk),
        .Reset_n(Reset_n),
        .Led(Led)
    );
    
    initial Clk = 1;
    always #10 Clk = !Clk;
    initial begin
        Reset_n = 0;
        #200;
        Reset_n = 1;
        #200000000;
    end
endmodule