FPGA入门学习笔记（七）Vivado之阻塞赋值非阻塞赋值

NonnettaWu

已于 2023-05-17 20:03:02 修改

阅读量489

点赞数 1

分类专栏： FPGA 文章标签： fpga开发学习

于 2023-03-04 15:54:24 首次发布

本文链接：https://blog.csdn.net/weixin_45463952/article/details/129308242

版权

FPGA 专栏收录该内容

21 篇文章 14 订阅

订阅专栏

仿真波形

在这里插入图片描述

设计文件程序

`timescale 1ns / 1ps
module block_unblock(
    input Clk,
    input Reset_n,
    input a,
    input b,
    input c,
    output reg [1:0]out
    );
    reg [1:0] d;
    always@(posedge Clk or negedge Reset_n)
    if(Reset_n == 0)begin
        out <= 0;
        d <= 0;
    end
    else begin
        out = d + c;
        d = a + b;
//        out <= d + c;
//        d <= a + b;  
    end
endmodule

仿真文件程序

`timescale 1ns / 1ns

module block_unblock_tb();
    reg Clk;
    reg Reset_n;
    reg a;
    reg b;
    reg c;
    wire [1:0]out;
    block_unblock block_test(
        .Clk(Clk),
        .Reset_n(Reset_n),
        .a(a),
        .b(b),
        .c(c),
        .out(out)
    );
    initial Clk <= 1;
    always #10 Clk <= !Clk;
    initial begin
        Reset_n <= 0;
        a = 0; b = 0; c = 0;
        #200;
        Reset_n = 1;
        #200;
        a = 0; b = 0; c = 0;
        #200;
        a = 0; b = 0; c = 1;
        #200;
        a = 0; b = 1; c = 0;
        #200;
        a = 0; b = 1; c = 1;
        #200;
        a = 1; b = 0; c = 0;
        #200;
        a = 1; b = 0; c = 1;
        #200;
        a = 1; b = 1; c = 0;
        #200;
        a = 1; b = 1; c = 1;
        #200;
        $stop;
    end
    
endmodule