verilog基础设计7-同步fifo的实现

1、同步fifo 的实现主要需要考虑以下几点

• empty 空信号
• full 满信号
• 什么时候读
• 什么时候写

2、 基于以上几点考虑开始书写verilog

module sy_fifo(
    input wire clk,
    input wire rst_n,
    input wire wr_en,
    input wire [7:0] data_in,
    input wire rd_en,
    output wire  full,
    output reg [7:0] data_out,
    output wire   empty
);

localparam deepth = 256;
localparam width  = 8;

reg [width-1:0] mem [deepth-1:0];
reg [8:0] count;
wire  wr;
wire  rd;
reg [7:0] rd_addr;
reg [7:0] wr_addr;

assign wr = (wr_en) && (~full);
assign rd = (rd_en) && (~empty);

//wr_addr ctrl
always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        wr_addr <= 8'd0;
    else if(wr)
        wr_addr <= wr_addr + 1'b1;
    else 
        wr_addr <= wr_addr;
end

//wr_data;
always @(posedge clk) begin
    if(wr)
        mem[wr_addr] <= data_in;
     else 
        mem[wr_addr] <= mem[wr_addr];
  
end

//rd_addr ctrl
always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        rd_addr <= 8'd0;
    else if(rd)
        rd_addr <= rd_addr +1'b1;
    else 
        rd_addr <= rd_addr;
end
 
// rd data;
always @(posedge clk or negedge rst_n) begin
    if(!rst_n) 
        data_out <= 8'd0;
    else if(rd)
        data_out <= mem[rd_addr];
    else 
        data_out <= data_out;
end

//count
always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        count <= 8'd0;
    else if(rd && ~wr && (count >=1))
        count <= count  - 1'd1;
    else if(wr && ~rd &&(count <=255))
        count <= count + 1'd1;
    else 
        count <= count;
end 

//full empty 

assign empty = (count == 8'd0) ? 1'b1:1'b0;

assign full = (count == 9'd256) ? 1'b1:1'b0;
endmodule 

3、进行仿真

`timescale 1ns/1ps
`define clock_period 20

module sy_fifo_tb;
reg clk;
reg rst_n;
reg wr_en;
reg rd_en;
reg [7:0] data_in;
wire [7:0] data_out;
wire full;
wire empty;

initial clk =1'b1;
always #(`clock_period/2) clk = ~clk;
integer i;
initial begin
    wr_en = 0;
    data_in =0;
    rst_n = 0;
    rd_en =0;
    #100;
    rst_n =1;
    #100;
    
    for (i =0;i<256;i=i+1)begin
        @(posedge clk)
            data_in = {$random}%256;
        wr_en = 1'b1;
        if(i== 128)
            rd_en =1;
    end
    #30;
    wr_en =0;
    
      
end


sy_fifo sy_fifo_inst(
    .clk(clk),
    .rst_n(rst_n),
    .wr_en(wr_en),
    .data_in(data_in),
    .rd_en(rd_en),
    .full(full),
    .data_out(data_out),
    .empty(empty)
);

endmodule

 4、进行测试，验证功能

empty 信号的产生

 数据读读出

 full信号产生

 到此，这个同步fifo功能基本正确