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最新推荐文章于 2024-07-29 22:25:40 发布

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分类专栏： verilog 文章标签： verilog

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module top_module (
    input clk,
    input reset,   // Synchronous reset
    input x,
    output z
);

    parameter s0 = 3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100;
    reg [2:0] state, next_state;
    
    always @(*)
        begin
            case(state)
                s0: next_state = x ? s1 : s0;
                s1: next_state = x ? s4 : s1;
                s2: next_state = x ? s1 : s2;
                s3: next_state = x ? s2 : s1;
                s4: next_state = x ? s4 : s3;
            endcase
        end
    
    always @(posedge clk)
        begin
            if(reset)
                state <= s0;
            else
                state <= next_state;
        end
    
    assign z = (state == s3 || state == s4);
endmodule