https://hdlbits.01xz.net/wiki/Exams/2014_q3bfsm
module top_module (
input clk,
input reset, // Synchronous reset
input x,
output z
);
parameter S0=0,S1=1,S2=2,S3=3,S4=4;
reg [2:0] cs,ns;
always@(*)
begin
case(cs)
S0:ns = x?S1:S0;
S1:ns = x?S4:S1;
S2:ns = x?S1:S2;
S3:ns = x?S2:S1;
S4:ns = x?S4:S3;
endcase
end
always@(posedge clk)
begin
if (reset)
cs<=S0;
else
cs<=ns;
end
assign z = (cs==S3)|(cs==S4);
endmodule