HDLBits学习：Exams/2014 q3fsm

题目：

Consider a finite state machine with inputs s and w. Assume that the FSM begins in a reset state called A, as depicted below. The FSM remains in state A as long as s = 0, and it moves to state B when s = 1. Once in state B the FSM examines the value of the input w in the next three clock cycles. If w = 1 in exactly two of these clock cycles, then the FSM has to set an output z to 1 in the following clock cycle. Otherwise z has to be 0. The FSM continues checking w for the next three clock cycles, and so on. The timing diagram below illustrates the required values of z for different values of w.

Use as few states as possible. Note that the s input is used only in state A, so you need to consider just the w input.

AI翻译：

考虑一个输入为 s 和 w 的有限状态机。假设 FSM 以称为 A 的重置状态开始， 如下图所示。只要 s = 0，FSM 就会保持状态 A，当 s = 1 时，它会变为状态 B。一旦进入状态 B，FSM 将在接下来的三个中检查输入 w 的值 时钟周期。如果在这些时钟周期中的两个时钟周期中 w = 1，则 FSM 必须在下一个时钟周期中将输出 z 设置为 1。否则 z 必须为 0。密克罗尼西亚联邦继续检查w 接下来的三个时钟周期，依此类推。下面的时序图说明了所需的值 对于不同的 W 值，Z 值。

使用尽可能少的状态。请注意，s 输入仅在状态 A 中使用，因此您只需考虑 w 输入。

状态转换图

分析：本题难点在于如何实现不断的三个周期查询w值并判断

解决办法：另外设置一个寄存器进行判断输出值，同时使三种状态不断循环

实现代码如下：

//Exams/2014 q3fsm
module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);

parameter A   = 2'd0;
parameter B_0 = 2'd1;
parameter B_1 = 2'd2;
parameter B_2 = 2'd3;

reg [1:0] state     ;
reg [1:0] next_state;
reg [31:0] cnt       ; 
//状态如何转换
always@(*)begin
    case(state)
    A  :next_state=s?B_0:A;
    B_0:next_state=B_1;    
    B_1:next_state=B_2;          
    B_2:next_state=B_0;            
    default:;
    endcase
end

always@(posedge clk)begin
    case(state)
    A  :cnt=1'd0;
    B_0:cnt=w?1'd1:1'd0;   
    B_1:cnt=cnt+w;             
    B_2:cnt=cnt+w;             
    default:;
    endcase
end

//状态何时转换
always @(posedge clk) begin
    if(reset)
    state<=A;
    else
    state<=next_state;  
end

assign z=(state==B_0&cnt==2);

endmodule