数字逻辑：75-23计数（减法）器（使用MAX+plus II 、Verilog语言 编写）

代码

module counter75_23(reset,clk,mid_H,mid_L,mid_L_cy);

    input reset,clk;
    output[3:0] mid_H,mid_L;		
    output mid_L_cy;
    reg[3:0] mid_H,mid_L;
    wire mid_L_cy;
    assign mid_L_cy=(mid_L==4'd0)?1:0;
    always @ (posedge clk)
		begin
        	if(reset) mid_L<=4'd5;
        	else if(mid_L==4'd3 & mid_H==4'd2) mid_L<=4'd5;
        	else if(mid_L_cy==1) 
                 begin
                     mid_L<=4'd9;
                 end
        	else mid_L<=mid_L-1;
    	end
    always @ (posedge clk)
		begin
        	if(reset) mid_H<=4'd7;
        	else if(mid_L==4'd3 & mid_H==4'd2) mid_H<=4'd7;
        	else if(mid_L_cy==1)
				begin
            		mid_H<=mid_H-1;
        		end
        	else mid_H<=mid_H;
		end

endmodule

说明

无