前言
简单对加法/减法计数器使用Verilog进行表述
减法计数器
always @ ( posedge CLK or posedge RST ) begin
if( RST ) begin
r_CNT <=9'd0 ;
end else begin
if (r_CNT != 9'd0) begin
r_CNT <= r_CNT - 1'b1 ;
end else if (s_SET) begin
r_CNT <= r_REG_SIZE[8:0];
end else begin
r_CNT <= r_CNT;
end
end
end