题目描述
You are given the following AND gate you wish to test:
module andgate (
input [1:0] in,
output out
);
Write a testbench that instantiates this AND gate and tests all 4 input combinations, by generating the following timing diagram:
代码
module top_module();
reg[1:0] in;
wire out;
initial
begin
in=2'b00;
#10 in=2'b01;
#10 in=2'b10;
#10 in=2'b11;
end
andgate g1(in,out);
endmodule