Verilog数字系统设计教程[第4版]夏宇闻——第三部分练习八

测试仿真流程

测试仿真环境为win系统下的quartus prime + modelsim
测试仿真流程参照我之前的教程
Verilog数字系统设计教程第4版夏宇闻——第三部分练习一

模块源代码

//----------seqdet.v----------
module seqdet(x,z,clk,rst,state);
input x,clk,rst;
output z;
output[2:0] state;
reg[2:0] state;
wire z;

parameter IDLE='d0,A='d1,B='d2,C='d3,D='d4,E='d5,F='d6,G='d7;

assign z = (state==E&&x==0)?1:0;
//x序列10010最后一个0刚到时刻，时钟沿立刻将状态变为E，此时z应该变为高
always@(posedge clk)
	if(!rst)
		begin
			state<=IDLE;
		end
	else
		casex(state)
			IDLE:
				if(x==1)
					state<=A;
			A:
				if(x==0)
					state<=B;
			B:
				if(x==0)
					state<=C;
				else
					state<=F;
			C:
				if(x==1)
					state<=D;
				else
					state<=G;
			D:
				if(x==0)
					state<=E;
				else
					state<=A;
			E:
				if(x==0)
					state<=C;
				else
					state<=A;
			F:
				if(x==1)
					state<=A;
				else
					state<=B;
			G:
				if(x==1)
					state<=F;
			default:
				state<=IDLE;
		endcase

endmodule

测试模块代码

//----------seqdet.vt----------
`timescale 1 ns/ 1 ns

module seqdet_vlg_tst();
reg clk;
reg rst;
reg[23:0] data;                                       
wire [2:0]  state;
wire x,z;

assign x = data[23];

always #10 clk = ~clk;
always@(posedge clk)
	data = {data[22:0],data[23]};
	
initial
	begin
		clk = 0;
		rst = 1;
		#2 rst = 0;
		#30 rst = 1;
		data = 'b1100_1001_0000_1001_0100;
		#500 $stop;
	end

seqdet i1 (
	.clk(clk),
	.rst(rst),
	.state(state),
	.x(x),
	.z(z)
);
                                                   
endmodule

结果波形