同步fifo代码（例化RAM）

module syn_fifo #(parameter FIFO_WIDTH = 32,
                  parameter FIFO_DEPTH = 16,
                  parameter ADDR_WIDTH = 4 )
        (
            input    wire                        clk    ,
            input    wire                        rst_n  ,
            input    wire                        wr_en  ,
            input    wire                        rd_en  ,
            input    wire   [FIFO_WIDTH-1 : 0]   wr_data,
            output   reg    [FIFO_WIDTH-1 : 0]   rd_data,
            output   wire                        wr_full,
            output   wire                        rd_empty
        );

        reg [ADDR_WIDTH:0] wr_addr, rd_addr;

        always @(posedge clk, negedge rst_n) begin
            if(~rst_n) begin
                wr_addr <= 'h0;
            end
            else if(wr_en && (~wr_full)) begin
                wr_addr <= wr_addr+1'b1;
            end
        end

        always @(posedge clk, negedge rst_n) begin
            if(~rst_n) begin
                rd_addr <= 'h0;
            end
            else if(rd_en && (~rd_empty)) begin
                rd_addr <= rd_addr+1'b1;
            end
        end

        assign wr_full = (wr_addr=={~rd_addr[ADDR_WIDTH],rd_addr[ADDR_WIDTH-1:0]});
        assign rd_empty = (wr_addr==rd_addr);

        dual_ram #(.RAM_WIDTH(FIFO_WIDTH),
                   .RAM_DEPTH(FIFO_DEPTH),
                   .ADDR_WIDTH(ADDR_WIDTH)) U_dual_ram
                   (
                    .wr_clk         (clk                    ),
                    .rd_clk         (clk                    ),
                    .rst_n          (rst_n                  ),
                    .wr_addr        (wr_addr[ADDR_WIDTH-1:0]),
                    .wr_en          (wr_en                  ),
                    .wr_data        (wr_data                ),
                    .rd_addr        (rd_addr[ADDR_WIDTH-1:0]),
                    .rd_en          (rd_en                  ),
                    .rd_data        (rd_data                )
                   );

endmodule

module dual_ram #(parameter RAM_WIDTH = 32,
                  parameter RAM_DEPTH = 16,
                  parameter ADDR_WIDTH = 4)
        (
            input   wire                        wr_clk ,
            input   wire                        rd_clk ,
            input   wire                        rst_n  ,
            //write signals
            input   wire   [ADDR_WIDTH-1:0]     wr_addr,
            input   wire                        wr_en  ,
            input   wire   [RAM_WIDTH-1:0]      wr_data, 
            //read signals
            input   wire   [ADDR_WIDTH-1:0]     rd_addr,
            input   wire                        rd_en  ,
            output  reg    [RAM_WIDTH-1:0]      rd_data   
        );

        reg [RAM_WIDTH-1:0] mem [0:RAM_DEPTH-1];
        integer i;

        always @(posedge wr_clk, negedge rst_n) begin
            if(~rst_n) begin
                for(i=0;i<RAM_DEPTH;i=i+1) begin
                    mem[i] <= 'h0;
                end
            end
            else if(wr_en) begin
                mem[wr_addr] <= wr_data;
            end
        end

        always @(posedge rd_clk, negedge rst_n) begin
            if(~rst_n) begin
                rd_data <= 'h0;
            end
            else if(rd_en) begin
                rd_data <= mem[rd_addr];
            end
        end
endmodule