开始的想法错误,只使用一个clk2并不能解决问题,需要一个posedge_clk2和negedge_clk2,分别完成单独的三分频后,进行或操作给clk2;
module f3(clk,rst,clk2);
input clk,rst;
output clk2;
reg [1:0]posedge_count;
reg [1:0]negedge_count;
reg posedge_clk2;
reg negedge_clk2;
always@(posedge clk or negedge rst)begin
if(!rst||posedge_count==2'b10)
posedge_count<=0;
else
posedge_count<=posedge_count+1'b1;
end
always@(negedge clk or negedge rst)begin
if(!rst||negedge_count==2'b10)
negedge_count<=0;
else
negedge_count<=negedge_count+1'b1;
end
always@(posedge clk or negedge rst)begin
if(!rst)
posedge_clk2<=0;
else if(posedge_count==0||posedge_count==1)
posedge_clk2<=!posedge_clk2;
else
posedge_clk2<=posedge_clk2;
end
always@(negedge clk or negedge rst)begin
if(!rst)
negedge_clk2<=0;
else if(negedge_count==0||negedge_count==1)
negedge_clk2<=!negedge_clk2;
else
negedge_clk2<=negedge_clk2;
end
assign clk2=negedge_clk2||posedge_clk2;
endmodule
testbench:
`timescale 1ns/1ps
module f3_tb();
reg clk;
reg rst;
wire clk2;
f3 u1(.clk(clk),.rst(rst),.clk2(clk2));
always begin
#5 clk=~clk;
end
initial begin
clk=0;
rst=0;
#5 rst=1;
#100
$stop;
end
endmodule