基于AHB协议的SRAMC设计（续）

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前言

这篇文章主要为解决上一篇文章中未解决的问题，完善之前设计中存在的缺陷。那就是写入后面紧跟一个读取时会导致无法正常读取，原因可以回顾上一篇文章。下面看详细的代码和解决思路。

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一、设计代码及分析

主要更改了ahb_slave_if中的代码，代码如下：

module ahb_slave_if (
  input hclk,
  input hrstn,
  input hsel,
  input hready,
  input hwrite,
  input [2:0]hburst,
  input [31:0]haddr,
  input [1:0]htrans,
  input [2:0]hsize,
  input [31:0]hwdata,
  input [31:0]rdata,
  output reg [31:0]hrdata,
  output reg [3:0]en,
  output write,
  output read,
  output [31:0]sram_addr,
  output reg [31:0]wdata,
  output reg hreadyout
);
//地址和控制信号寄存器
  reg [31:0] haddr_r;
  reg [2:0]  hsize_r;
  reg hwrite_r;
  reg [2:0]hburst_r;
  reg [1:0]htrans_r;

  always@(posedge hclk or negedge hrstn)begin
    if(!hrstn)begin
      haddr_r  <= 0;
      hsize_r  <= 0;
      hwrite_r <= 0;
      hburst_r <= 0;
      htrans_r <= 0;
    end
    else if(hsel&&hready)begin
      haddr_r  <= haddr;
      hsize_r  <= hsize;
      hwrite_r <= hwrite;
      hburst_r <= hburst;
      htrans_r <= htrans;
    end
    else begin
      haddr_r  <= 0;
      hsize_r  <= 0;
      hwrite_r <= 0;
      hburst_r <= 0;
      htrans_r <= 0;
    end
  end
//等待处理
  reg hwait;
  always@(*)
    if((!hwrite && hwrite_r) || !hreadyout)
      hwait = 1;
    else
      hwait = 0;
//读写信号控制
  wire hwrite_wait;
  assign hwrite_wait = (!hwait) ? hwrite : hwrite_wait;

  reg hwrite_wait_r;
  always@(posedge hclk or negedge hrstn)
    if(!hrstn)
      hwrite_wait_r <= 0;
    else if(hsel && hready)
      hwrite_wait_r <= hwrite_wait;
    else
      hwrite_wait_r <= 0;
  
  assign write = (htrans_r==2'b10 || htrans_r==2'b11) && hwrite_wait_r;
  assign read  = (htrans==2'b10 || htrans==2'b11) && (!hwrite_wait_r);


//地址处理

  wire [31:0] haddr_wait;
  assign haddr_wait = (!hwait) ? haddr : haddr_wait;

  reg [31:0