HDL—Verilog Language—Procedures—Avoiding latches

Suppose you're building a circuit to process scancodes from a PS/2 keyboard for a game.   Given the last two bytes of scancodes received, you need to indicate whether one of the arrow keys on the keyboard have been pressed.   This involves a fairly simple mapping, which can be implemented as a case statement (or if-elseif) with four cases.

假设你正在为一个游戏构建一个处理PS/2键盘扫描代码的电路。给定接收到的扫描码的最后两个字节，你需要指出是否按下了键盘上的一个方向键。这涉及到一个相当简单的映射，可以实现为具有四种情况的case语句(或if-elseif)。

scancode[15:0]	arrow key
16'he06b	left arrow
16'he072	down arrow
16'he074	right arrow
16'he075	up arrow
Anything else	none

其实还是case语句而已，但要注意每次输出之后，要把几个按键的值恢复到0.

// synthesis verilog_input_version verilog_2001
module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  );
    always@(*)begin
        left <= 0;
        down <= 0;
        right <= 0;
        up <= 0;
        case(scancode)
            16'he06b : left <= 1;
            16'he072 : down <= 1;
            16'he074 : right <= 1;
            16'he075 : up <= 1;
            default : ;
        endcase
    end
endmodule