Modelsim远程无法打开异常处理

在远程桌面打开Modelsim时,我们无法打开,会弹出:Fatal License Error错误,其原因为:在License文件中,没有允许远程访问;所以我们只需要在 Modelsim的license文件中增加允许远程打开即可;
【报错图片】
在这里插入图片描述

【解决办法】

  1. 打开Modelsim的license文件;
  2. 在所有的INCREMENT 句子的末尾增加 TS_OK;
  3. 问题解决;

技巧:由于该License中有一千多句需要增加 TS_OK, 可以使用文本编辑器,例如:SUBLIME, pycharm等软件,使用替换功能;
查找:"$ // 这句话的意思是寻找以"结尾的句子末尾;
替换:"TS_OK

方法如下:
在这里插入图片描述

以INCERMENT开头的语句,都需要增加TS_OK结尾:
在这里插入图片描述
变更后的License:
在这里插入图片描述

【问题解决】远程时,软件正常打开
在这里插入图片描述

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Mentor, a Siemens business, has unveiled ModelSim 10.7, is unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment. About Mentor Graphics ModelSim. Modelsim HDL simulator provides FPGA customers with and easy cost-effective way to speed up FPGA development, lab bring up and test. Many FPGA designers go to the lab before adequately vetting their design. This means weeks or even months of inefficient debugging time in the lab. Testing in the lab has limited visibility of the signals in design. It can take 8 hours to do a place and route just instrument additional signals or make a small bug fix. With simulation the debug loop is much faster and there is complete visibility into the signals in the design. Simulation enables a much higher quality FPGA design before entering the lab allowing time spent during lab debug much more productive and focused. In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code. The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).

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