HDLbits---Verilog Language----Basics

1.Simple wire

module top_module( input in, output out );
assign out=in;
endmodule

2.Four wires

module top_module( 
    input a,b,c,
    output w,x,y,z );
assign w=a;
    assign x=b;
    assign y=b;
    assign z=c;
endmodule

3.Inverter

module top_module( input in, output out );
assign out=~in;
endmodule

4.AND gate

module top_module( 
    input a, 
    input b, 
    output out );
assign out=a&&b;
endmodule

5.NOR gate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out=~(a||b);
endmodule

6.XNOR gate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out=~(a^b);
endmodule

7.Declaring wires

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
wire A, B, C;
    assign A=a&&b;
    assign B=c&&d;
    assign C=A||B;
    assign out=C;
    assign out_n=~C;
endmodule

8.7458 chip

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
wire a,b,c,d;
    assign a=p2a&&p2b;
    assign b=p2c&&p2d;
    assign c=p1a&&p1b&&p1c;
    assign d=p1d&&p1e&&p1f;
    assign p2y=a||b;
    assign p1y=c||d;
endmodule