verilog报错

1，Critical Warning (10191): Verilog HDL Compiler Directive warning at ref_sdram.v(9): text macro "ASIZE" is undefined

`include "相对路径"

放在.v文件的第一行，如果上方命令引用该文件的参数，则会报错。

define用法：`define   ASIZE  13

2,Error (10839): Verilog HDL error at Sdram_Params.h(8): declaring global objects is a SystemVerilog feature

需要将include放进module模块，所以输入输出管脚用到文件定义的参数时，格式如下：

module 模块名

（输入，

    输出）；

`include "相对路径"

input 输入;

output（reg）输出;

3，Warning (10762): Verilog HDL Case Statement warning at ref_sdram.v(77): can't check case statement for completeness because the case expression has too many possible states

参数定义位宽过大

4，Error (10134): Verilog HDL Module Declaration error at sdram_init.v(14): port "rst_n" is declared more than once

module （）；      定义参数时少加，