Verilog module模块练习题

学习FPGA Verilog语言 遇到的习题，记录下相关代码，以便以后复习查阅。

模块习题
题目1：
You are given a module my_dff with two inputs and one output (that implements a D flip-flop). Instantiate three of them, then chain them together to make a shift register of length 3. The clk port needs to be connected to all instances.

The module provided to you is: module my_dff ( input clk, input d, output q );

Note that to make the internal connections, you will need to declare some wires. Be careful about naming your wires and module instances: the names must be unique.

题目分析：创建三个模块，配置不同的输入输出。

module top_module ( input clk, input d, output q );

	wire q12;
    wire q23;
    
    my_dff dff1(clk,d,q12);
    my_dff dff2(clk,q12,q23);
    my_dff dff3(clk,q23,q);
    
endmodule

题目2：
You are given a module my_dff8 with two inputs and one output (that implements a set of 8 D flip-flops). Instantiate three of them, then chain them together to make a 8-bit wide shift register of length 3. In addition, create a 4-to-1 multiplexer (not provided) that chooses what to output depending on sel[1:0]: The value at the input d, after the first, after the second, or after the third D flip-flop. (Essentially, sel selects how many cycles to delay the input, from zero to three clock cycles.)

The module provided to you is: module my_dff8 ( input clk, input [7:0] d, output [7:0] q );

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    wire [7:0] A,B,C;
    
    my_dff8 dff1(clk,d,A);
    my_dff8 dff2(clk,A,B);
    my_dff8 dff3(clk,B,C);
    
    always @(*)
        case(sel)
            2'b00 : q = d;
            2'b01 : q = A;
            2'b10 : q = B;
            2'b11 : q = C;
        endcase

endmodule

官方solution：

module top_module (
	input clk,
	input [7:0] d,
	input [1:0] sel,
	output reg [7:0] q
);

	wire [7:0] o1, o2, o3;		// output of each my_dff8
	
	// Instantiate three my_dff8s
	my_dff8 d1 ( clk, d, o1 );
	my_dff8 d2 ( clk, o1, o2 );
	my_dff8 d3 ( clk, o2, o3 );

	// This is one way to make a 4-to-1 multiplexer
	always @(*)		// Combinational always block
		case(sel)
			2'h0: q = d;
			2'h1: q = o1;
			2'h2: q = o2;
			2'h3: q = o3;
		endcase

endmodule

题目3：
Connect the modules together as shown in the diagram below. The provided module add16 has the following declaration:

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

我的解答：

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire	[0:0]	add12; //定义第一个加法器与第二个加法器的连接线
    wire	[15:0]	sum1;  //定义第一个加法器的输出线
    wire	[31:16]	sum2;  //定义第二个加法器的输出线
    add16 add16_inst1(
        .a(a[15:0])		,
        .b(b[15:0])		,
        .cout(add12)    ,
        .sum(sum1)	
    );
    add16 add16_inst2(
        .a(a[31:16])	,
        .b(b[31:16])	,
        .cin(add12)	    ,
        .sum(sum2)
    );
    assign sum   = {sum2,sum1}; //将两个输出用位拼接接起来，赋值给顶层模块的输出
   
endmodule

题目4：
Within each add16, 16 full adders (module add1, not provided) are instantiated to actually perform the addition. You must write the full adder module that has the following declaration:

module add1 ( input a, input b, input cin, output sum, output cout );

Recall that a full adder computes the sum and carry-out of a+b+cin.

In summary, there are three modules in this design:

top_module — Your top-level module that contains two of…
add16, provided — A 16-bit adder module that is composed of 16 of…
add1 — A 1-bit full adder module.

我的解答：

module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);//

    wire [0:0] add12;
    wire [15:0] sum11;
    wire [31:16] sum12;
    
    add16 add1(
        .a(a[15:0]),
        .b(b[15:0]),
        .cout(add12),
        .sum(sum11)
    );
    
    add16 add2(
        .a(a[31:16]),
        .b(b[31:16]),
        .cin(add12),
        .sum(sum12)
    );
    
    assign sum = {sum12,sum11};
    
endmodule

module add1 ( input a, input b, input cin,   output sum, output cout );

    assign {cout,sum} = a + b + cin;

endmodule

题目5：
Connect the modules together as shown in the diagram below. The provided module add16 has the following declaration:

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

我的解答：

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
	
    wire [15:0] sum1;
    wire [15:0] sum2;
    wire [0:0] sel;
    wire [15:0] sum11;
    
    add16 add1(
        .a(a[31:16]),
        .b(b[31:16]),
        .cin(1'b0),
        .sum(sum1)
    );
    
    add16 add2(
        .a(a[31:16]),
        .b(b[31:16]),
        .cin(1'b1),
        .sum(sum2)
    );
    
    add16 add3(
        .a(a[15:0]),
        .b(b[15:0]),
        .cin(1'b0),
        .sum(sum11),
        .cout(sel)
    );
    
    always @(*)
        case (sel)
            1'b0 : sum = {sum1,sum11};
            1'b1 : sum = {sum2,sum11};
        endcase
endmodule

题目6：
Build the adder-subtractor below.

You are provided with a 16-bit adder module, which you need to instantiate twice:

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

Use a 32-bit wide XOR gate to invert the b input whenever sub is 1. (This can also be viewed as b[31:0] XORed with sub replicated 32 times. See replication operator.). Also connect the sub input to the carry-in of the adder.

module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);

    wire	[31:0] 	xor_wire; //定义经过xor门后的输出线   
    wire	[0:0]	add12; //定义第一个加法器与第二个加法器的连接线
    wire	[15:0]	sum1;  //定义第一个加法器的输出线
    wire	[31:16]	sum2;  //定义第二个加法器的输出线
    
    assign xor_wire = {32{sub}}^b;
    
    add16 add1(
    	.a(a[15:0])			,
        .b(xor_wire[15:0])	,
        .cin(sub)			,
        .cout(add12)  		,
        .sum(sum1)
    );
	
    add16 add2(
        .a(a[31:16])			,
        .b(xor_wire[31:16])	,
        .cin(add12)			,
        .sum(sum2)
    );
    
    assign sum = {sum2,sum1};
    
endmodule

题目7：