Verilog更多练习题
本文章旨在练习后记录,方便之后复习查阅,如有错误,欢迎斧正。
题目1:
Given four unsigned numbers, find the minimum. Unsigned numbers can be compared with standard comparison operators (a < b). Use the conditional operator to make two-way min circuits, then compose a few of them to create a 4-way min circuit. You’ll probably want some wire vectors for the intermediate results.
我的解答:
module top_module (
input [7:0] a, b, c, d,
output [7:0] min);//
// assign intermediate_result1 = compare? true: false;
wire [7:0] min1;
wire [7:0] min2;
wire [7:0] min3;
assign min1 = (a < b) ? a : b;
assign min2 = (min1 < c) ? min1 : c;
assign min3 = (min2 < d)? min2 : d;
assign min = min3;
endmodule
题目2:
Parity checking is often used as a simple method of detecting errors when transmitting data through an imperfect channel. Create a circuit that will compute a parity bit for a 8-bit byte (which will add a 9th bit to the byte). We will use “even” parity, where the parity bit is just the XOR of all 8 data bits.
我的解答:
module top_module (
input [7:0] in,
output parity);
assign parity = ^in[7:0];
endmodule
题目3:
Build a combinational circuit with 100 inputs, in[99:0].
There are 3 outputs:
out_and: output of a 100-input AND gate.
out_or: output of a 100-input OR gate.
out_xor: output of a 100-input XOR gate.
我的解答:
module top_module(
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = & in[99:0];
assign out_or = | in[99:0];
assign out_xor = ^in[99:0];
endmodule
题目4:
Given a 100-bit input vector [99:0], reverse its bit ordering.
提示:A for loop (in a combinational always block or generate block) would be useful here. I would prefer a combinational always block in this case because module instantiations (which require generate blocks) aren’t needed.(用always语句和for循环。)
我的解答:
module top_module(
input [99:0] in,
output [99:0] out
);
always @(*)
begin
int i;
for(i=0;i<100;i++)
out[i] = in[100-i-1];
end
endmodule
官方solution:
module top_module (
input [99:0] in,
output reg [99:0] out
);
always @(*) begin
for (int i=0;i<$bits(out);i++) // $bits() is a system function that returns the width of a signal.
out[i] = in[$bits(out)-i-1]; // $bits(out) is 100 because out is 100 bits wide.
end
endmodule
解释:$bits() is a system function that returns the width of a signal.
其系统函数功能为返回信号宽度。
题目5:
A “population count” circuit counts the number of '1’s in an input vector. Build a population count circuit for a 255-bit input vector.
module top_module(
input [254:0] in,
output [7:0] out );
always @(*)begin
out = 0;
for(int i=0;i<255;i++)
out = out + in[i];
end
endmodule
官方solution:
module top_module (
input [254:0] in,
output reg [7:0] out
);
always @(*) begin // Combinational always block
out = 0;
for (int i=0;i<255;i++)
out = out + in[i];
end
endmodule
题目6:
Create a 100-bit binary ripple-carry adder by instantiating 100 full adders. The adder adds two 100-bit numbers and a carry-in to produce a 100-bit sum and carry out. To encourage you to actually instantiate full adders, also output the carry-out from each full adder in the ripple-carry adder. cout[99] is the final carry-out from the last full adder, and is the carry-out you usually see.
我的解答:
module top_module(
input [99:0] a, b,
input cin,
output [99:0] cout,
output [99:0] sum );
assign {cout[0],sum[0]} = a[0] + b[0] + cin;
generate
genvar i;
for(i=1;i<100;i++)
begin: full
full_adder adder1(
.a(a[i]),
.b(b[i]),
.cin(cout[i-1]),
.cout(cout[i]),
.sum(sum[i])
);
end
endgenerate
endmodule
module full_adder(
input a,
input b,
input cin,
output cout,
output sum
);
assign {cout, sum} = a + b + cin;
endmodule
分析:了解generate语句的作用。
题目7:You are provided with a BCD one-digit adder named bcd_fadd that adds two BCD digits and carry-in, and produces a sum and carry-out.
module bcd_fadd {
input [3:0] a,
input [3:0] b,
input cin,
output cout,
output [3:0] sum );
Instantiate 100 copies of bcd_fadd to create a 100-digit BCD ripple-carry adder. Your adder should add two 100-digit BCD numbers (packed into 400-bit vectors) and a carry-in to produce a 100-digit sum and carry out.
我的解答:
module top_module(
input [399:0] a, b,
input cin,
output cout,
output [399:0] sum );
wire [99:0] line;
bcd_fadd add1(
.a(a[3:0]),
.b(b[3:0]),
.cout(line[0]),
.cin(cin),
.sum(sum[3:0])
);
generate
genvar i;
for(i=1;i<100;i++) begin: bcd_fadd_inst1
bcd_fadd bcd_fadd_inst(
.a(a[(7+4*(i-1)) : (4+4*(i-1))]),
.b(b[(7+4*(i-1)) : (4+4*(i-1))]),
.cout(line[i]),
.cin(line[i-1]),
.sum(sum[(7+4*(i-1)):(4+4*(i-1))])
);
end
endgenerate
assign cout = line[99];
endmodule
思考:generate语句作用是将其中写的模块展开后像数组一样。