Verilog HDL 高级数字设计实验

1、在软件中输入代码
module Register_File#(parameter word_size=32,addr_size=5)
(output [word_size-1:0] Data_Out_1,Date_Out_Out_2,
input [word_size-1:0] Data_in,
input [addr_size-1:0] Read_Addr_1, Read_Addr_2, Write_Addr,
input Write_Enable,Clock);
reg [word_size-1: 0] Reg_File [31: 0]; //32bit x32 word memory declaration

assign   Data_Out_1=Reg_File[Read_Addr_1];
assign   Date_Out_Out_2=Reg_File[Read_Addr_2];

always @ (posedge Clock) begin
if  (Write_Enable == 1'b1) 
Reg_File [Write_Addr]<=Data_in;
end

endmodule
2、输入测试代码
`timescale 1 ps/ 1 ps
module Register_File_vlg_tst();

reg Clock;
reg [31:0] Data_in;
reg [4:0] Read_Addr_1;
reg [4:0] Read_Addr_2;
reg [4:0] Write_Addr;
reg Write_Enable;

wire [31:0] Data_Out_1;
wire [31:0] Date_Out_Out_2;

Register_File i1 (

.Clock(Clock),
.Data_Out_1(Data_Out_1),
.Data_in(Data_in),
.Date_Out_Out_2(Date_Out_Out_2),
.Read_Addr_1(Read_Addr_1),
.Read_Addr_2(Read_Addr_2),
.Write_Addr(Write_Addr),
.Write_Enable(Write_Enable)

);
initial
Data_in [31:0]=32’hffffffff;
initial
begin
Clock=1’b0;
Write_Enable=1’b1;
#10 Write_Enable=1’b0;
#50 Write_Enable=1’b1;
#10 Write_Enable=1’b0;
#50 Write_Enable=1’b1;
#10 Write_Enable=1’b0;
#100 Write_Enable=1’b1;
#10 Write_Enable=1’b0;
#200 $stop;
end
always #5 Clock = ~Clock;
initial
begin
Read_Addr_1[4:0]=4’b0000;
#20 Read_Addr_1=4’b0001;
#40 Read_Addr_1=4’b0010;
#60 Read_Addr_1=4’b0011;
#110 Read_Addr_1=4’b0110;
#200 $stop;
end
initial
begin
Read_Addr_2[4:0]=4’b0000;
#80 Read_Addr_2=4’b0001;
#40 Read_Addr_2=4’b0010;
#10 Read_Addr_2=4’b0011;
#100 Read_Addr_2=4’b0110;
#200 $stop;
end
initial
begin
Write_Addr[4:0]=4’b0000;
#80 Write_Addr=4’b0001;
#40 Write_Addr=4’b0010;
#10 Write_Addr=4’b0011;
#100 Write_Addr=4’b0110;
#200 $stop;
end
endmodule

3、编译运行出结果

4、实验视频
https://www.bilibili.com/video/BV1V44y1z7rE?share_source=copy_web
5、总结：1、代码输入还是慢，花费比较多时间。
2、测试代码不会写，需要在课后多多练习。