LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY NBITSHIFT IS
GENERIC(N:INTEGER:=8);
PORT(
CLK,DIN:IN STD_LOGIC;
QOUT:OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)
);
END NBITSHIFT;
ARCHITECTURE RTL OF NBITSHIFT IS
SIGNAL TEMP:STD_LOGIC_VECTOR(N-1 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
TEMP(0)<=DIN;
TEMP(N-1 DOWNTO 1)<=TEMP(N-2 DOWNTO 0);
/*还有一种方法,如下:
FOR I IN 0 TO N-2 LOOP
TEMP(I+1)<=TEMP(I);
END LOOP;
*/
END IF;
END PROCESS;
QOUT<=TEMP;
END RTL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY GENSIGANL IS
PORT(
CLK:IN STD_LOGIC;
YOUT:OUT STD_LOGIC
);
END GENSIGNAL;
ARCHITECTURE RTL OF GENSIGANL IS
SIGNAL Q1,Q2,Q3,Q4:STD_LOGIC;
SIGNAL D1,D2,D3,D4:STD_LOGIC;
BEGIN
YOUT<=Q4;
D1<=((Q3)XOR(Q4))OR((NOT Q1)AND(NOT Q2)AND(NOT Q3)AND(NOT Q4));
D2<=Q1;
D3<=Q2;
D4<=Q3;
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
Q1<=D1;
Q2<=D2;
Q3<=D3;
Q4<=D4;
END IF;
END PROCESS;
END RTL;
LIBRARY IEEE;
IEEE.STD_LOGIC_1164.ALL;
ENTITY BISHIFT IS
PORT(
CLR,DIR,CLK,LOAD:IN STD_LOGIC;
DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
QOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END BISHIFT;
ARCHITECTURE RTL OF BISHIFT IS
SIGNAL DREG:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(CLR,CLK)
BEGIN
IF CLR='0' THEN DREG<="00000000";
ELSIF CLK'EVENT AND CLK='1' THEN
IF LOAD='0' THEN DREG<=DIN;
ELSE
IF DIR='0' THEN
DREG(0)<=DREG(7);
FOR I IN 0 TO 6 LOOP
DREG(I+1)<=DREG(I);
END LOOP;
ELSE DREG(7)<=DREG(0);
DREG(6 DOWNTO 0)<=DREG(7 DOWNTO 1);
END IF;
END IF;
END IF;
END PROCESS;
QOUT<=DREG;
END RTL;