HDLbits笔记

Circuits----Sequential Logic

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前言

一、题目（FSM-serial receiver）

In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One common scheme is to use one start bit (0), 8 data bits, and 1 stop bit (1). The line is also at logic 1 when nothing is being transmitted (idle).

Design a finite state machine that will identify when bytes have been correctly received when given a stream of bits. It needs to identify the start bit, wait for all 8 data bits, then verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte.

二、解决

1.常规设置状态转移

代码如下（示例）：

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
    parameter s0=0, s1=1,s2=2, s3=3, s4=4, s5=5, s6=6, s7=7, s8=8, s9=9, s10=10, s11=11;
    wire [3:0] state, next;
    
    // state transition logic
    always@(*)begin
        case(state)
            s0: next = in? s0:s1;
            s1: next = s2;
            s2: next = s3;
            s3: next = s4;
            s4: next = s5;
            s5: next = s6;
            s6: next = s7;
            s7: next = s8;
            s8: next = s9;
            s9: next = in? s10:s11;
            s10: next = in? s0:s1;
            s11: next = in? s0:s11;
        endcase
    end
    
    // flip-flop and reset
    always@(posedge clk)begin
        if(reset)
            state <= s0;
        else
            state <= next;
    end
    
    //output
    assign done = (state == s10);
    
endmodule

2.使用计数器（可以应用到多位数据传输）

用计数器替换中间数据传输的状态过程
代码如下（示例）：

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
    parameter s0=0,s1=1,s2=2,s3=3,s4=4;
    reg [3:0]state,next_state;
    reg [2:0]count;
    always@(posedge clk)begin
        if(reset)
            state<=1'b0;
        else
            state<=next_state;
    end
    always@(posedge clk)begin
         if(state==s1)
            count<=count+1'b1;
        else
            count<=1'b0;
    end
    always@(*)begin
        case(state)
            s0:next_state=in?s0:s1;
            s1:next_state=(count==3'b111)?s2:s1;
            s2:next_state=in?s3:s4;
            s3:next_state=in?s0:s1;
            s4:next_state=in?s0:s4;
        endcase
    end
    
    assign done=(state==s3);

endmodule

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总结