RAM波形叠加时序

最新推荐文章于 2024-05-20 19:26:01 发布

60岁退休老大爷

最新推荐文章于 2024-05-20 19:26:01 发布

阅读量72

点赞数

文章标签： fpga开发

本文链接：https://blog.csdn.net/weixin_61892350/article/details/131719044

版权

{signal: [
  ['input',
  	{name: 'clk', wave: 'P...................|...',         period: 1},     
 	{name: 'rst', wave: 'l.H.................|...'},
  ],
  ['inside',
     {name: 'stack_en', wave: 'l..1............|...',         phase: 0 },
   {name: 'state', wave: '2..2222222222........|...', data:['','s0','s1','s2','s3','s4','s5','s6','s7','s8'],       phase: 0 },
    {name: 'rd_clk', wave: 'h...LhLh............|...',         phase: 0 },
    {name: 'rd_addr', wave: '2..2.2.2..........|...',  data:['','rd_addr0','rd_addr1'],       phase: 0 },
 	{name: 'rd_data', wave: '2..2.2.2..........|...',  data:['','rd_data0','rd_data1'],       phase: 0 },
    {name: 'cnt_rd_data', wave: '1....0.1.........|...',  data:['','rd_data0','rd_data1'],       phase: 0 },
     {name: 'wr_clk', wave: 'h.......lHlH........|...',         phase: 0 },
     {name: 'wr_addr', wave: '2.......2.2.2.......|...',  data:['','wr_addr0','wr_addr1'],       phase: 0 },
    {name: 'wr_data', wave: '2.......2.2.2.......|...',  data:['','wr_data0','wr_data1'],       phase: 0 },
       {name: 'cnt_wr_data', wave: '1.......0.1.........|...',  data:['','rd_data0','rd_data1'],       phase: 0 },
  ],
  ['output',
  	{name: 'xxx', wave: 'l...................|...',         phase: 0.5 },
  ],
 
],
head: {text:
  ['tspan',
    ['tspan', {class:'error h3'}, '双口RAM读写控制时序'],
  ],
},
   config: { hscale:  1}
}