Verilog语言——HDLBits刷题记录

Verilog语言——HDLBits刷题记录

基础

Simple wire

Create a module with one input and one output that behaves like a wire.

Four wires

Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections:

a -> w
b -> x
b -> y
c -> z

Inverter

Create a module that implements a NOT gate.

AND gate

Create a module that implements an AND gate.

NOR gate

Create a module that implements a NOR gate. A NOR gate is an OR gate with its output inverted. A NOR function needs two operators when written in Verilog.

XNOR gate

Create a module that implements an XNOR gate.

Declaring wires

The circuits so far have been simple enough that the outputs are simple functions of the inputs. As circuits become more complex, you will need wires to connect internal components together. When you need to use a wire, you should declare it in the body of the module, somewhere before it is first used. (In the future, you will encounter more types of signals and variables that are also declared the same way, but for now, we’ll start with a signal of type wire).

7458 chip

The 7458 is a chip with four AND gates and two OR gates.

总结

以上就是基础部分的刷题记录，属于非常基础的一些的操作！！！