Quartus II 实现偶分频

期末裸考系列之 偶分频（10分频）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity DIV is
	port (clk : in std_logic;
           k : out std_logic); 
end entity;
architecture one of DIV is 
	signal c : std_logic_vector(2 downto 0);
	signal m : std_logic;
begin
process(clk, c)  begin 
	if rising_edge(clk) then
	if (c = "100") then c <= "000";m <= not m; else c <= c+1; end if;

	end if; 
end process;

	k <= m;
end  one;