【VCS】常见VCS编译Warning总结

1.Warning-[UII-L] Interfaec not instantiated

Interface ‘xxx_interfeace’ defined in logic library ‘work’ is never instantiated design.It will be ingored

工程中某些定义的interface没有被实例化，验证平台搭建中比较常见，可忽略。

2.Warning-[PCWM-W] Port connection width mismatch

……
The following 32-bit expression is connection to 1-bit port

有时候此类warning出现在对module例化过程中，比如直接对某一个1-bit的端口直接tie 0便会报此warning，改写为1’b0便可以消除此warning

3.UVM_WARNING @1.00ns reporter [CMPNFD] Component matching

‘xx.xx.amba_env_die0’ was not found in the list of uvm_components
Error-[NOA] Null object access

特别常见的一种空对象错误，报错的本质体现在WARNING中，引用路径中为发现amba_env_die0没有例化，但是自己确实在sub_env中例化了amba_env啊，为什么有问题？仔细一下，例化的时候名称为amba_env_d0。(多么愚蠢的错误！！！)

4.Warning-[DRTZ] Detect delay value roundoff to 0

Delay from design or SDF file roundoff to 0 based on timescale
Please check dumped diagnostic file (timescale.txt)

开发代码中使用延时被四舍五入为0导致。在编译过程中会产生timescale.txt文件，内部会详细记录具体是哪个module，以及该module的timescale

5.Warning-[SVA-TIDE] $time in disable iff

arm_clken_mon, “assert_CLK_EN_CHECK” $time is used in the disable iff expression. A change in time alone will not trigger assertion evaluation.

断言中在disable iff中使用到了$time 或 $realtime