![](https://i-blog.csdnimg.cn/blog_migrate/454a062f320b101b7c68e424f54ac2a0.png)
verilog实现上面的电路:
module pulse_syc(
input sclk_1,
input sclk_2,
input p_in,
output p_out,
output p_out1
);
reg p_in_reg=0;
reg delay0,delay1,delay2;
wire mux_2;
assign mux_2=(p_in==1'b1)?~p_in_reg:p_in_reg;
input sclk_1,
input sclk_2,
input p_in,
output p_out,
output p_out1
);
reg p_in_reg=0;
reg delay0,delay1,delay2;
wire mux_2;
assign mux_2=(p_in==1'b1)?~p_in_reg:p_in_reg;
always@(posedge sclk_1)
p_in_reg<=mux_2;
assign p_out1=p_in_reg;
always@(posedge sclk_2)
{delay2,delay1,delay0}<={delay1,delay0,p_in_reg};
assign p_out=delay2^delay1;
endmodule
p_in_reg<=mux_2;
assign p_out1=p_in_reg;
always@(posedge sclk_2)
{delay2,delay1,delay0}<={delay1,delay0,p_in_reg};
assign p_out=delay2^delay1;
endmodule
使用条件:输入脉冲的间隔至少是两个同步器时钟周期
快时钟到慢时钟仿真结果:
间隔两个同步器时钟周期时:
![](https://i-blog.csdnimg.cn/blog_migrate/858a24ddd38dcd9ee52c32fdad86b662.png)
间隔小于两个同步器时钟周期时:
![](https://i-blog.csdnimg.cn/blog_migrate/49f7f065540510fc0dbbdf79823bbe46.png)
慢时钟到快时钟仿真结果:
间隔大于两个同步器时钟:
![](https://i-blog.csdnimg.cn/blog_migrate/a44f50b005531c9f475be740f2c02f10.png)
间隔小于两个同步器时钟:
![](https://i-blog.csdnimg.cn/blog_migrate/910de7559d8c0c9296bf169ede4ef33b.png)