FPGA设计中MEMORY型数据怎么综合到blockRAM里面

在Synplicity综合可以在你定义数组的后面加上综合语句，
比如reg [7:0] mem[15:0] /* synthesis syn_ramstyle="block_ram" */;后面“”中也可以是MLAB、M9K、M144K、no_rw_check等，根据你的芯片选择，具体可以看Synplicity的帮助文档。

在ise中在定义前使用attribute ram_stype :block_ram语句，具体和Synplicity差不多。

ramstyle Verilog HDL Synthesis Attribute

A Verilog HDL synthesis attribute that controls the way an inferred RAM is implemented.

Note: Analysis & Synthesis also recognizes the synonymous synthesis attribute syn_ramstyle. This synthesis attribute behaves identically to the ramstyle synthesis attribute.

To use the ramstyle attribute in a Verilog Design File (.v), specify the synthesis attribute delimited by (* and *) preceding the Variable Declaration of an inferred RAM whose implementation you want to control. Specify the synthesis attribute value as “logic”, “M512”, “M4K”, “M9K”, “M20K”, “M144K”, “MLAB”, or “M-RAM” depending on the type of memory block you want the Quartus II software to use when implementing the inferred RAM. If you use the synthesis attribute on anything but a variable that represents a RAM, or if you specify an illegal value, the Quartus II software ignores that synthesis attribute.

By setting the value to “M512”, “M4K”, “M9K”, “M20K”, “M144K”, “MLAB”, or “M-RAM”, you can choose the type of memory block that the Quartus II software uses when implementing the inferred RAM. If the attribute is set to “logic”, then the RAM is implemented in logic cells.

In addition to specifying the type of memory block for the RAM implementation, by setting the value to “no_rw_check”, you can use the ramstyle attribute to indicate that you do not care about the output of the inferred RAM when there are simultaneous reads and writes to the same address. By default, the Quartus II software tries to create an inferred RAM with the same read-during-write behavior as your HDL source. In some cases, a RAM must be mapped into logic because it has a read-during-write behavior that is not supported by the memory blocks in your target device. In other cases, the Quartus II software must insert extra logic to mimic your read-during-write behavior, which can increase the resource requirements or reduce the performance of your design. Setting the “no_rw_check” value directs the Quartus II Compiler that the read-during-write behavior of the HDL source does not need to be preserved.

Note: You can specify both a block-type and “no_rw_check” in a single attribute by separating the values with a comma, for example “no_rw_check, M512”, or you can specify only a block-type or “no_rw_check”.

For example, in the following code, the ramstyle synthesis attribute specifies that the inferred RAM my_ram should be implemented using an M512 memory block:

(* ramstyle = “M512” *) reg [0:7] my_ram[0:63];

Note: You can also embed the ramstyle synthesis attribute in a comment following the Variable Declaration of an inferred RAM, as shown in the following code:
reg [0:7] my_ram[0:63] /* synthesis ramstyle = “M512” */;