有符号64位的点定数加法,带进位,随机化测试,平台vcs
加法器代码
//20180827
//add 64bit
module adder_64bit(
input wire [63:0]a_in,
input wire [63:0]b_in,
input wire c_in,
output c_out,
output [63:0]sum_out
);
//有符号加法
assign {c_out,sum_out}={a_in[63],a_in}+{b_in[63],b_in}+{
{64{c_in}},c_in};//signed adder
//无符号加法
//assign {c_out,sum_out}={1'b0,a_in}+{1'b0,b_in}+{64'd0,c_in};//signed adder unsigned add
endmodule
testbench代码
//adder_64bit tb
//20180827 9:15
module adder_64bit_tb();
reg [63:0]ain;
reg [63:0]bin;
reg cin;
wire cout;
wire [63:0]sumout;
adder_64bit u_adder_64bit(//例化
.a_in(ain),
.b_in(bin),
.c_in(cin),
.c_out(cout),
.sum_out(sumout)
);
parameter CLK_P=20;//宏
reg clk,rst_n;
//input CLK_PERIOD
/*integer cycle_num;
initial begin
if(!$value$plusargs("cycle_num=%d