lk/arch/crt0.s中的_start函数为入口函数,crt0.s主要初始化CPU,然后长跳转(bl)到lk/kernel/main.c中kmain函数。
- lk的代码起始位置在crt0.S中。
#define DSB .byte 0x4f, 0xf0, 0x7f, 0xf5
#define ISB .byte 0x6f, 0xf0, 0x7f, 0xf5
.section ".text.boot"
.globl _start // 声明全局符号_start
_start: // _start中值即为当前地址
// 设置异常向量表,从0地址开始,存放在8*4字节的连续内存中。需要将协处理CP15中的c1控制寄存器的中的V位配为0
b reset // 跳转到reset
b arm_undefined
b arm_syscall
b arm_prefetch_abort
b arm_data_abort
b arm_reserved
b arm_irq
b arm_fiq
reset:
#ifdef ENABLE_TRUSTZONE // makefile中ENABLE_TRUSTZONE := 0,因此不用关心
/*Add reference to TZ symbol so linker includes it in final image */
ldr r7, =_binary_tzbsp_tzbsp_bin_start
#endif
/* do some cpu setup */
#if ARM_WITH_CP15
/* Read SCTLR */
mrc p15, 0, r0, c1, c0, 0 // MCR/MRC{cond} P15,opcode_1,Rd,CRn,CRm,opcode_2 读取cp15协处理器的寄存器1(Control register)的值到通用寄存器r0中
/* XXX this is currently for arm926, revist with armv6 cores */
/* new thumb behavior, low exception vectors, i/d cache disable, mmu disabled */
bic r0, r0, #(1<<15| 1<<13 | 1<<12) // 位清除指令,Low addresses = 0x00000000, ICache disabled
bic r0, r0, #(1<<2 | 1<<0) // DCache disabled, MMU disabled
/* disable alignment faults */
bic r0, r0, #(1<<1) // Data address alignment fault checking disabled
/* Enable CP15 barriers by default */
#ifdef ARM_CORE_V8
orr r0, r0, #(1<<5)
#endif
/* Write SCTLR */
mcr p15, 0, r0, c1, c0, 0 // 将设置好的r0的值写入到p15的寄存器1中,完成关闭MMU,禁用ICahce和DCache等。
#ifdef ENABLE_TRUSTZONE
/*nkazi: not needed ? Setting VBAR to location of new vector table : 0x80000 */
ldr r0, =0x00080000
mcr p15, 0, r0, c12, c0, 0
#endif
#endif
#if WITH_CPU_EARLY_INIT // 目前使用的soc都没有打开此宏,因此不去关注
/* call platform/arch/etc specific init code */
#ifndef ENABLE_TRUSTZONE
/* Not needed when TrustZone is the first bootloader that runs.*/
bl __cpu_early_init
#endif
/* declare return address as global to avoid using stack */
.globl _cpu_early_init_complete
_cpu_early_init_complete:
#endif
#if (!ENABLE_NANDWRITE)
#if WITH_CPU_WARM_BOOT // 目前使用的soc都没有打开此宏,因此不去关注
ldr r0, warm_boot_tag
cmp r0, #1
/* if set, warm boot */
ldre