ERROR: [Constraints 18-642]

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AR# 62761

Vivado 2014.3 : ERROR: [Constraints 18-642] Placement is not routable as design contains luts and/or flops

 

描述

My design is completely routed in Vivado 2014.1 without any error.

Vivado 2014.3 returns an error at placement and fails implementation.

 

 ERROR: [Constraints 18-642] Placement is not routable as design contains luts and/or flops whose data pins are driven by global clock signals and final placement is such that the number of such signals exceed the maximum allowable in a single tile. Only a maximum number of 5 distinct global clocks can drive data pins of SLICE resources in a single tile. The following clock nets need to be routed to non-clock pins in tile CLBLL_L_X2Y58: 
delay_clk_gen_inst_1/inst/clk_out3, delay_clk_gen_inst_1/inst/clk_out5, delay_clk_gen_inst_1/inst/clk_out4, delay_clk_gen_inst_1/inst/clk_out2, delay_clk_gen_inst_1/inst/clk_out6, delay_clk_gen_inst_1/inst/clk_out7, and delay_clk_gen_inst_1/inst/clk_out1 
ERROR: [Constraints 18-646] Placement is not routable. The following cell(s) are grouped together and are placed in one single tile. The total number of clocks on non-clock pins of these cells is greater than 5, therefore, placer is not able to legalize the design to satisfy the suggested number of clocks that can drive non-clock pins in a single tile. Please modify the design such that each cell has at most 2 clocks driving its non-clock pins. Also, if one or more cells should be grouped together and placed in one tile, make sure the total number of such clocks does not exceed the maximum suggested.

解决方案

 

The feasibility check can be overly restrictive. 

The routability of non-clock pins from global resources is complicated and the feasibility check is set at a conservative level to guarantee routability.

 

The following parameter has been added in the 2015.1 release to override the limit: 
 

set_param place.skipGFANChecks true

 

Use of this parameter will not guarantee routability, but will allow you to attempt it.