fpga布线笔记

fpga布线笔记

刚开始研究fpga布线，当时认为vivado的布线器是笨的，感觉舍近求远，选择长的路线来布而不选短的，

在xilinx论坛里发帖问了一大堆，每次都能得到很热心的回复，甚至觉得几乎都是秒回的，

那里有两个大神id是avrumv 和drjohnsmith，几乎我的每个帖子他俩都来回了，而且一回就是一大堆，比我发的帖子写得还多

1    同一个Slice里的4个LUT是内部不互联的，并不是想当然地认为，应该是连通的，内部连通net delay应该就等于0

同一个CLB的两个Slice也是不连通的，

尝试强制手动布线，报类似如下的错

 [Vivado 12-2285] Cannot set LOC property of instance 'b_reg[6]',  for bel A5FF Element SLICE_X59Y74.AFFMUX is not routable,  for bel B5FF Element SLICE_X59Y74.BFFMUX is not routable,  for bel C5FF Element SLICE_X59Y74.CFFMUX is not routable,  for bel D5FF Element SLICE_X59Y74.DFFMUX is not routable [D:/tishi/bitstream_verilog_20191112_rbsp_buffer_2byte_merge/project_1/xdc.xdc:37]

Resolution: When using BEL constraints, ensure the BEL constraints are defined before the LOC constraints to avoid conflicts at a given site.

所以一个slice的LUT连到另一个LUT，需要先连出去，经过switch，然后再回来这样绕一圈。

     Within the CLB there is no LUT to LUT connection (at least not until Versal!),

 so a net is required to leave the CLB, travel to the switch matrix, and, at best, travel back to the same CLB. This route is virtually identical between any two LUTs in the CLB (two slices). In your case, the second LUT is in an adjacent CLB, so instead of going through one switch matrix it goes through two using only a "single" vertical route - this is the 2nd fastest route you can have in the FPGA.

2    线路图只是给大致的示意图，实际芯片是很复杂的，图中看起来很长的路径，实际net delay可能很短，看起来很短的路径实际net delay可能很长，

下图中红色highlight的这条路径延迟是0.298, 黄色highlight的这条路径延迟是0.818

3    最短路径net delay=0的，来自上下相邻的两个slice，如下图中的这两个slice，而红圈里的两个slice是同一个CLB里的两个slice，是互不联通的。

net delay为0的，是Y上相邻的，同一个X，即上下2个CLB, 如果逻辑级数有10级，但是每级fanout都是1，那理论上从最上的CLB一直连到最下的CLB，可以N多级，net一路为0，

之前尝试过用pblock，把一些unit框住固定位置,手动布线等等，效果都不佳，老老实实从代码入手，来减少fanout。

布线尽量少干预，让布线器自己来，他是聪明的，除非你比他更聪明。

把大神的建议都贴在这里

 As for your specific question - it is virtually impossible to know why the tool gives the placement it does. The placement process is an immense problem - the number of combinations of possible placements is unimaginably huge (literally). The tools use heuristics to come up with a placement that minimizes the cost function (which is a combination of WNS, total route length, and congestion). However, since this is an NP complete problem, the best it can do is find a local minimum.

 So looking at one particular placement on its own is meaningless - if you were to get the tools to disrupt this one placement, you would end up disrupting the entire design - most likely ending up with a worse final solution.

It show the silicon / metalisation is inside the chips.

There are multiple layers of routing options inside the chips,

Once upon a time,routing was easy , and us users could actually go in there and twiddle the "pips" to move signals on to different route structures.

The last 20 years that has not been practical.

You have to design by constraiing the desing and letting the tools work out the routes that meet your constraints.

The big thing there, that lots of people, even those experienced don't get, is the tools do not find the "Best" route, they just meet your design constraints and stop.

And the Silicon is way more complex inside than the simple GUI presentations one sees, thats all part of the IP of Xilinx,

So as to why two seemingly similar routes have different delays is somethign your never going to find out unless you delve deep into the silicon / metalisation, and I dont think Xilxin are going to give away those secrets.

If its really important to your company about the differences in the delays, then talk to your FAE.

They can set up NDA's , and then depths of information is limited only by how deep your pockets are.