xdma 2019.2 simulation in verdi

Makefile:

CUR_DIR = $(shell pwd)
PRJ_DIR = ${CUR_DIR}/..
export PRJ_DIR

note =
export note

SIM_DIR = proj_simu_${note}
export SIM_DIR

.PHONY: vcs verdi test

vcs:
    rm -rf ${SIM_DIR}; \
    mkdir ${SIM_DIR}; \
    cd ${SIM_DIR}; \
    ../vcs.sh

verdi:
    cd ${SIM_DIR}; \
    verdi -sv -nologo -autoalias -dbdir simv.daidir -ssf inter.fsdb &

test:
    cd ${PRJ_DIR} && pwd

vcs.sh:

export TOP_NAME=board
export TOP_HIER=board

echo "----------------------------------------------------------------"
echo "----------------------------------------------------------------"
echo "-- Simulator : vcs-mx 2018.09"
echo "-- top module: $TOP_NAME"
echo "----------------------------------------------------------------"
echo "----------------------------------------------------------------"

touch synopsys_sim.setup

vivado -nojournal -mode tcl -source ../vivado.tcl -tclargs vcs

vlogan -full64 -debug_access+all -sverilog -kdb -lca -work WORK +v2k +vcs+lic+wait -timescale=1ns/1ps \
    -f ${PRJ_DIR}/simulate/verdi.f ${XILINX_VIVADO}/data/verilog/src/glbl.v -error=noMPD

vcs -full64 -debug_access+all -sverilog -kdb -lca WORK.${TOP_HIER} WORK.glbl -LDFLAGS -Wl,--no-as-needed \
    -P ${VERDI_HOME}/share/PLI/VCS/LINUX64/novas.tab ${VERDI_HOME}/share/PLI/VCS/LINUX64/pli.a -l elaborate.log

./simv -l simu.log -ucli -do ../vcs.tcl

vivado.tcl:

compile_simlib -language verilog -library unisim -family virtex7 -no_ip_compile -simulator [lindex $argv 0] -directory vivado_libs
exit

verdi.f:

+incdir+${PRJ_DIR}/imports

${PRJ_DIR}/imports/pcie3_uscale_rp_top.v
${PRJ_DIR}/imports/pci_exp_usrapp_tx.v
${PRJ_DIR}/imports/pcie3_uscale_rp_core_top.v
${PRJ_DIR}/imports/pci_exp_usrapp_com.v
${PRJ_DIR}/imports/board.v
${PRJ_DIR}/imports/xilinx_pcie_uscale_rp.v
${PRJ_DIR}/imports/pci_exp_usrapp_rx.v
${PRJ_DIR}/imports/xdma_app.v
${PRJ_DIR}/imports/sys_clk_gen.v
${PRJ_DIR}/imports/pci_exp_usrapp_cfg.v
${PRJ_DIR}/imports/sys_clk_gen_ds.v
${PRJ_DIR}/imports/pci_exp_usrapp_pl.v
${PRJ_DIR}/imports/xilinx_dma_pcie_ep.sv


${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/blk_mem_gen_0/sim/blk_mem_gen_0.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/blk_mem_gen_0/simulation/blk_mem_gen_v8_4.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/blk_mem_gen_1/sim/blk_mem_gen_1.v

// ${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/xdma_0_sim_netlist.v

${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/sim/xdma_0.sv

+incdir+${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/hdl/verilog
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/hdl/xdma_v4_1_vl_rfs.sv

${XILINX_VIVADO}/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv
${XILINX_VIVADO}/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv
${XILINX_VIVADO}/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv

${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/xdma_v4_1/hdl/verilog/xdma_0_core_top.sv
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/xdma_v4_1/hdl/verilog/xdma_0_dma_bram_wrap_1024.sv
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/xdma_v4_1/hdl/verilog/xdma_0_dma_bram_wrap.sv

${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/sim/xdma_0_pcie3_ip.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_qpll_drp.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_gt_common.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pcie_7vx.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pipe_clock.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pipe_sync.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pcie_bram_7vx_8k.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pipe_rate.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pcie_bram_7vx_16k.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_qpll_wrapper.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_rxeq_scan.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pipe_drp.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pcie_tlp_tph_tbl_7vx.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pcie_bram_7vx_rep.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pcie_3_0_7vx.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pcie_pipe_lane.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pcie_bram_7vx.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pcie_pipe_pipeline.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pipe_eq.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pcie_init_ctrl_7vx.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pcie_bram_7vx_rep_8k.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pipe_wrapper.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pcie_force_adapt.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pipe_reset.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pipe_user.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pcie_bram_7vx_req.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pcie_bram_7vx_cpl.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_gt_top.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pcie_pipe_misc.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_gtx_cpllpd_ovrd.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_qpll_reset.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_pcie_top.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_0/source/xdma_0_pcie3_ip_gt_wrapper.v

${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v
${PRJ_DIR}/xdma_0_ex.srcs/sources_1/ip/xdma_0/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v


-f ${XILINX_VIVADO}/data/secureip/pcie_3_1/pcie_3_1_cell.list.f
-f ${XILINX_VIVADO}/data/secureip/gthe3_channel/gthe3_channel_cell.list.f
-f ${XILINX_VIVADO}/data/secureip/gthe3_common/gthe3_common_cell.list.f

vcs.tcl:
 

fsdbDumpfile   "inter.fsdb"
fsdbDumpvars 0 "$env(TOP_HIER)" +mda

run 1ms