逻辑stream一阶的实现

module pipe_stage_1 #(
    parameter integer             DATA_WIDTH = 32
) (
    input  logic                  clk,
    input  logic                  rst_n,

    output logic                  in_ready,
    input  logic                  in_valid,
    input  logic [DATA_WIDTH-1:0] in_data,

    input  logic                  out_ready,
    output logic                  out_valid,
    output logic [DATA_WIDTH-1:0] out_data
);

// -------------------------------------------

logic reg_flag;
logic pre_to_nxt;
logic enable_to_nxt;

assign in_ready = ~reg_flag;
assign enable_to_nxt = ~{&{~out_ready, out_valid}};
assign pre_to_nxt = &{|{in_valid, reg_flag}, enable_to_nxt};

always_ff@(posedge clk `ifdef ASYNC_RST or negedge rst_n `endif) begin
    if(!rst_n) begin
        reg_flag <= 1'b0;
        out_valid <= 1'b0;
    end else begin
        reg_flag <= (reg_flag) ? (~enable_to_nxt) : (&{in_valid, ~enable_to_nxt});
        out_valid <= (enable_to_nxt) ? pre_to_nxt : out_valid;
    end
end

logic [DATA_WIDTH-1:0] reg_data;

always_ff @ (posedge clk) begin
    reg_data <= (reg_flag) ? reg_data : in_data;
    out_data <= (~enable_to_nxt) ? out_data : ((reg_flag) ? reg_data : in_data);
end

// -------------------------------------------
    
endmodule