state fsm demo

logic state_is_idle;
logic state_is_run;
logic state_is_end;

localparam IDLE = 3'b001;
localparam RUN  = 3'b010;
localparam END  = 3'b100;

reg [2:0] state;
reg [2:0] next_state;
assign {state_is_end, state_is_run, state_is_idle};

wire [1:0] input_vector;
assign input_vector = {the_out, the_enable};

always_comb begin
    casex ({state, input_vector})
        {IDLE, 2'bX1}: next_state = RUN;
        {RUN,  2'b1X}: next_state = END;
        {END,  2'bXX}: next_state = IDLE;
        default: next_state = state;
    endcase
end
    
always_ff@(posedge clk) begin
    if(!rst_n) begin
        state <= IDLE;
    end else begin
        state <= next_state;
    end
end