vivado ip with systemC model in vcs simulation

最新推荐文章于 2024-05-02 19:07:46 发布

xiuminxu

最新推荐文章于 2024-05-02 19:07:46 发布

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分类专栏：脚本 fpga 文章标签： shell fpga开发

本文链接：https://blog.csdn.net/xiuminxu/article/details/137843615

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this is an example, vivado ip with systemC model in vcs simulation

脚本：


echo "----------------------------------------------------------------"
echo "----------------------------------------------------------------"
echo "-- Simulator : vcs-mx 2018.09"
echo "-- top module: $TOP_NAME"
echo "----------------------------------------------------------------"
echo "----------------------------------------------------------------"

touch synopsys_sim.setup

vivado -nojournal -mode tcl -source ../vivado.tcl -tclargs vcs

syscan -cpp ${ROOT_DIR}/try_part/gcc-6.2.0-modified/gcc-6.2.0/install/bin/g++ -l sysc.log \
        ${CUR_DIR}/ip/axi_clock_converter_0/sim/axi_clock_converter_0.cpp \
        ${CUR_DIR}/ip/axi_clock_converter_0/sim/axi_clock_converter_0_sc.cpp \
        ${CUR_DIR}/ip/axi_clock_converter_0/sysc/axi_clock_converter.cpp \
        ${CUR_DIR}/ip/axi_clock_converter_1/sim/axi_clock_converter_1.cpp \
        ${CUR_DIR}/ip/axi_clock_converter_1/sim/axi_clock_converter_1_sc.cpp \
        ${CUR_DIR}/ip/axi_crossbar_0/sim/axi_crossbar_0.cpp \
        ${CUR_DIR}/ip/axi_crossbar_0/sim/axi_crossbar_0_sc.cpp \
        ${CUR_DIR}/ip/axi_crossbar_0/src/axi_crossbar.cpp \
        ${CUR_DIR}/ip/axi_dwidth_converter_0/sim/axi_dwidth_converter_0.cpp \
        ${CUR_DIR}/ip/axi_dwidth_converter_0/sim/axi_dwidth_converter_0_sc.cpp \
        ${CUR_DIR}/ip/axi_dwidth_converter_0/src/axi_dwidth_converter.cpp \
        ${CUR_DIR}/ip/axi_protocol_converter_0/sim/axi_protocol_converter_0.cpp \
        ${CUR_DIR}/ip/axi_protocol_converter_0/sim/axi_protocol_converter_0_sc.cpp \
        ${CUR_DIR}/ip/axi_protocol_converter_0/src/axi_protocol_converter.cpp \
        ${CUR_DIR}/ip/ddr4_0/sim/ddr4_0.cpp \
        ${CUR_DIR}/ip/ddr4_0/sim/ddr4_0_sc.cpp \
        ${CUR_DIR}/ip/ddr4_0/sim_tlm/top/sim_ddr_v2_0.cpp \
        ${CUR_DIR}/ip/hbm_0/sim/hbm_0.cpp \
        ${CUR_DIR}/ip/hbm_0/sim/hbm_0_sc.cpp \
        ${CUR_DIR}/ip/hbm_0/sysc/src/hbm_fmodel_base.cxx \
        ${CUR_DIR}/ip/hbm_0/sysc/src/hbm_fmodel_shared_memory.cxx \
        ${CUR_DIR}/ip/hbm_0/sysc/src/hbm_sc.cpp \
        ${CUR_DIR}/ip/hbm_0/sysc/src/hbmChannel.cpp \
        ${CUR_DIR}/ip/hbm_0/sysc/src/hbmModel.cpp

vlogan -full64 -debug_access+all -sverilog -kdb -lca -work WORK +v2k +vcs+lic+wait -timescale=1ns/1ps \
        -cpp ${ROOT_DIR}/try_part/gcc-6.2.0-modified/gcc-6.2.0/install/bin/g++ \
        +define+EXPORT_CXLMEM +define+EXPORT_BARMEM -f ${CUR_DIR}/verdi.f \
        ${PRJ_DIR}/ref_design/source/cxl_device_type3_cpi/bench/stimuli_m0.sv \
        ${XILINX_VIVADO}/data/verilog/src/glbl.v

vcs -full64 -debug_access+all -sverilog -sysc -kdb -lca WORK.${TOP_HIER} WORK.glbl -LDFLAGS -Wl,--no-as-needed \
        -cpp ${ROOT_DIR}/try_part/gcc-6.2.0-modified/gcc-6.2.0/install/bin/g++ -sysc=adjust_timeres \
        -P ${VERDI_HOME}/share/PLI/VCS/LINUX64/novas.tab ${VERDI_HOME}/share/PLI/VCS/LINUX64/pli.a -l elaborate.log

./simv -gui=verdi -l simu.log -ucli -do ../vcs.tcl

IP related:

+define+XILINX_SIMULATOR

// ${CUR_DIR}/ip/axi_clock_converter_0/sim/axi_clock_converter_0.v
// ${CUR_DIR}/ip/axi_clock_converter_0/sim/axi_clock_converter_0.cpp
${CUR_DIR}/ip/axi_clock_converter_0/sim/axi_clock_converter_0_stub.sv
// ${CUR_DIR}/ip/axi_clock_converter_0/sim/axi_clock_converter_0_sc.cpp

// ${CUR_DIR}/ip/axi_clock_converter_0/sysc/axi_clock_converter.cpp

// ${CUR_DIR}/ip/axi_clock_converter_1/sim/axi_clock_converter_1.v
// ${CUR_DIR}/ip/axi_clock_converter_1/sim/axi_clock_converter_1.cpp
${CUR_DIR}/ip/axi_clock_converter_1/sim/axi_clock_converter_1_stub.sv
// ${CUR_DIR}/ip/axi_clock_converter_1/sim/axi_clock_converter_1_sc.cpp

// ${CUR_DIR}/ip/axi_crossbar_0/sim/axi_crossbar_0.v
// ${CUR_DIR}/ip/axi_crossbar_0/sim/axi_crossbar_0.cpp
${CUR_DIR}/ip/axi_crossbar_0/sim/axi_crossbar_0_stub.sv
// ${CUR_DIR}/ip/axi_crossbar_0/sim/axi_crossbar_0_sc.cpp
// ${CUR_DIR}/ip/axi_crossbar_0/src/axi_crossbar.cpp

// ${CUR_DIR}/ip/axi_dwidth_converter_0/sim/axi_dwidth_converter_0.v
// ${CUR_DIR}/ip/axi_dwidth_converter_0/sim/axi_dwidth_converter_0.cpp
${CUR_DIR}/ip/axi_dwidth_converter_0/sim/axi_dwidth_converter_0_stub.sv
// ${CUR_DIR}/ip/axi_dwidth_converter_0/sim/axi_dwidth_converter_0_sc.cpp
// ${CUR_DIR}/ip/axi_dwidth_converter_0/src/axi_dwidth_converter.cpp

// ${CUR_DIR}/ip/axi_protocol_converter_0/sim/axi_protocol_converter_0.v
// ${CUR_DIR}/ip/axi_protocol_converter_0/sim/axi_protocol_converter_0.cpp
${CUR_DIR}/ip/axi_protocol_converter_0/sim/axi_protocol_converter_0_stub.sv
// ${CUR_DIR}/ip/axi_protocol_converter_0/sim/axi_protocol_converter_0_sc.cpp
// ${CUR_DIR}/ip/axi_protocol_converter_0/src/axi_protocol_converter.cpp

${CUR_DIR}/ip/clk_wiz_0/clk_wiz_0.v
${CUR_DIR}/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v

// ${CUR_DIR}/ip/ddr4_0/sim/ddr4_0.cpp
${CUR_DIR}/ip/ddr4_0/sim/ddr4_0_stub.sv
// ${CUR_DIR}/ip/ddr4_0/sim/ddr4_0_sc.cpp
// ${CUR_DIR}/ip/ddr4_0/sim_tlm/top/sim_ddr_v2_0.cpp

// ${CUR_DIR}/ip/hbm_0/sim/hbm_0.sv
// ${CUR_DIR}/ip/hbm_0/sim/hbm_0.cpp
${CUR_DIR}/ip/hbm_0/sim/hbm_0_stub.sv
// ${CUR_DIR}/ip/hbm_0/sim/hbm_0_sc.cpp

// ${CUR_DIR}/ip/hbm_0/sysc/src/hbm_fmodel_base.cxx
// ${CUR_DIR}/ip/hbm_0/sysc/src/hbm_fmodel_shared_memory.cxx
// ${CUR_DIR}/ip/hbm_0/sysc/src/hbm_sc.cpp
// ${CUR_DIR}/ip/hbm_0/sysc/src/hbmChannel.cpp
// ${CUR_DIR}/ip/hbm_0/sysc/src/hbmModel.cpp
${CUR_DIR}/ip/hbm_0/verif/model/hbm_model.sv
+incdir+${CUR_DIR}/ip/hbm_0/verif/model

-v ${XILINX_VIVADO}/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv
-v ${XILINX_VIVADO}/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv
-v ${XILINX_VIVADO}/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv