set device xcu280-fsvh2892-2L-e
set project_top "ref_design_top"
set project_dir "proj_hw_${project_top}_$env(timer)_$env(note)"
set debug_ila 1
file delete -force ${project_top}
file mkdir ${project_dir}
create_project -force ${project_top} ${project_dir} -part ${device}
set_property top ${project_top} [current_fileset]
read_verilog [glob dir/*.v]
set_property verilog_dir {dir/include} [current_fileset]
# read_ip
read_verilog "tmp.v"
read_xdc "top.xdc"
set_property flow {Vivado Synthesis 2023} [get_runs synth_1]
set_property strategy Flow_PerfOptimized_high [get_runs synth_1]
#set_property strategy Flow_AlternateRoutability [get_runs synth_1]
set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-verilog_define PIPE_AXI_NUM=$env(pipe_axi_num)} -objects [get_runs synth_1]
#set_property STEPS.SYNTH_DESIGN.ARGS.FANOUT_LIMIT "5000" [get_runs synth_1]
launch_runs synth_1
wait_on_run synth_1
open_run synth_1
if {$debug_ila>0} {
add ila signal
}
opt_design -directive Explore > $project_dir/opt_design.log
if {$debug_ila>0} {
write_debug_probes $project_dir/debug_nets.ltx
}
set_property strategy Performance_ExplorePostRoutePhysOpt [get_runs impl_1]
#set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
#set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE AdvancedSkewModeling [get_runs impl_1]
#set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
#set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
launch_runs impl_1
wait_on_run impl_1
open_run impl_1
report_high_fanout_nets -file "${project_dir}/fanout.rpt"
report_clock_utilization -file "${project_dir}/clock_utilization.rpt"
report_utilization -hierarchical -file "${project_dir}/utilization.rpt"
report_timing_summary -file "${project_dir}/timing_summary.rpt"
report_timing -sort_by group -nworst 50 -path_type full -file "${project_dir}/timing.rpt"
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
write_bitstream -force "${project_dir}/${project_top}.bit" > ${project_dir}/write_bitstream.log
if [expr {[get_property SLACK [get_timing_paths -delay_type min_max]] < -0.05}] {
puts "ERROR: Timing failed"
}
exit
vivado non-project mode demo
最新推荐文章于 2024-07-12 17:02:39 发布