/********************************************************************************************************* * Five channels Decodre_Input which is being coded & tested by tiger *********************************************************************************************************/ module decoder_test(clk, PB, condition, quadA, quadB, count); input clk; input [23:0] PB; //24 bits switchs input input [4:0] quadA, quadB; // 5 channels input input [2:0] condition; // 8 kinds of condition at most output [15:0] count; /*********************************************************************************************************/ reg [2:0] quadA_delayed0; reg [2:0] quadB_delayed0; reg [2:0] quadA_delayed1; reg [2:0] quadB_delayed1; reg [2:0] quadA_delayed2; reg [2:0] quadB_delayed2; reg [2:0] quadA_delayed3; reg [2:0] quadB_delayed3; reg [2:0] quadA_delayed4; reg [2:0] quadB_delayed4; /*********************************************************************************************************/ always @(posedge clk) quadA_delayed0 <= {quadA_delayed0[1:0], quadA[0]}; always @(posedge clk) quadB_delayed0 <= {quadB_delayed0[1:0], quadB[0]}; always @(posedge clk) quadA_delayed1 <= {quadA_delayed1[1:0], quadA[1]}; always @(posedge clk) quadB_delayed1 <= {quadB_delayed1[1:0], quadB[1]}; always @(posedge clk) quadA_delayed2 <= {quadA_delayed2[1:0], quadA[2]}; always @(posedge clk) quadB_delayed2 <= {quadB_delayed2[1:0], quadB[2]}; always @(posedge clk) quadA_delayed3 <= {quadA_delayed3[1:0], quadA[3]}; always @(posedge clk) quadB_delayed3 <= {quadB_delayed3[1:0], quadB[3]}; always @(posedge clk) quadA_delayed4 <= {quadA_delayed4[1:0], quadA[4]}; always @(posedge clk) quadB_delayed4 <= {quadB_delayed4[1:0], quadB[4]}; /*********************************************************************************************************/ wire count_enable0 = quadA_delayed0[1] ^ quadA_delayed0[2] ^ quadB_delayed0[1] ^ quadB_delayed0[2]; wire count_direction0 = quadA_delayed0[1] ^ quadB_delayed0[2]; wire count_enable1 = quadA_delayed1[1] ^ quadA_delayed1[2] ^ quadB_delayed1[1] ^ quadB_delayed1[2]; wire count_direction1 = quadA_delayed1[1] ^ quadB_delayed1[2]; wire count_enable2 = quadA_delayed2[1] ^ quadA_delayed2[2] ^ quadB_delayed2[1] ^ quadB_delayed2[2]; wire count_direction2 = quadA_delayed2[1] ^ quadB_delayed2[2]; wire count_enable3 = quadA_delayed3[1] ^ quadA_delayed3[2] ^ quadB_delayed3[1] ^ quadB_delayed3[2]; wire count_direction3 = quadA_delayed3[1] ^ quadB_delayed3[2]; wire count_enable4 = quadA_delayed4[1] ^ quadA_delayed4[2] ^ quadB_delayed4[1] ^ quadB_delayed4[2]; wire count_direction4 = quadA_delayed4[1] ^ quadB_delayed4[2]; /*********************************************************************************************************/ reg [15:0] count_buf0; reg [15:0] count_buf1; reg [15:0] count_buf2; reg [15:0] count_buf3; reg [15:0] count_buf4; //reg [15:0] count_buf5; //reg [15:0] count_buf6; /*********************************************************************************************************/ always @(posedge clk) begin if(count_enable0) begin if(count_direction0) count_buf0<=count_buf0+8'b0000_0001; else count_buf0<=count_buf0-8'b0000_0001; end end /*********************************************************************************************************/ always @(posedge clk) begin if(count_enable1) begin if(count_direction1) count_buf1<=count_buf1+8'b0000_0001; else count_buf1<=count_buf1-8'b0000_0001; end end /*********************************************************************************************************/ always @(posedge clk) begin if(count_enable2) begin if(count_direction2) count_buf2<=count_buf2+8'b0000_0001; else count_buf2<=count_buf2-8'b0000_0001; end end /*********************************************************************************************************/ always @(posedge clk) begin if(count_enable3) begin if(count_direction3) count_buf3<=count_buf3+8'b0000_0001; else count_buf3<=count_buf3-8'b0000_0001; end end /*********************************************************************************************************/ always @(posedge clk) begin if(count_enable4) begin if(count_direction4) count_buf4<=count_buf4+8'b0000_0001; else count_buf4<=count_buf4-8'b0000_0001; end end /*********************************************************************************************************/ //dispose the switch value /*********************************************************************************************************/ // First use two flipflops to synchronize the PB signal the "clk" clock domain /*********************************************************************************************************/ //PB0 reg PB0_sync_0; always @(posedge clk) PB0_sync_0 <= ~PB[0]; // invert PB to make PB_sync_0 active high reg PB0_sync_1; always @(posedge clk) PB0_sync_1 <= PB0_sync_0; /*********************************************************************************************************/ //PB1 reg PB1_sync_0; always @(posedge clk) PB1_sync_0 <= ~PB[1]; // invert PB to make PB_sync_0 active high reg PB1_sync_1; always @(posedge clk) PB1_sync_1 <= PB1_sync_0; /*********************************************************************************************************/ //PB2 reg PB2_sync_0; always @(posedge clk) PB2_sync_0 <= ~PB[2]; // invert PB to make PB_sync_0 active high reg PB2_sync_1; always @(posedge clk) PB2_sync_1 <= PB2_sync_0; /********************************************************************************