/********************************************************************************************************* * Five channels Decodre_Input which is being coded & tested by tiger *********************************************************************************************************/ module decoder_test(clk, PB, condition, quadA, quadB, count); input clk; input [23:0] PB; //24 bits switchs input input [4:0] quadA, quadB; // 5 channels input input [2:0] condition; // 8 kinds of condition at most output [15:0] count; /*********************************************************************************************************/ reg [2:0] quadA_delayed0; reg [2:0] quadB_delayed0; reg [2:0] quadA_delayed1; reg [2:0] quadB_delayed1; reg [2:0] quadA_delayed2; reg [2:0] quadB_delayed2; reg [2:0] quadA_delayed3; reg [2:0] quadB_delayed3; reg [2:0] quadA_delayed4; reg [2:0] quadB_delayed4; /*********************************************************************************************************/ always @(posedge clk) quadA_delayed0 <= {quadA_delayed0[1:0], quadA[0]}; always @(posedge clk) quadB_delayed0 <= {quadB_delayed0[1:0], quadB[0]}; always @(posedge clk) quadA_delayed1 <= {quadA_delayed1[1:0], quadA[1]}; always @(posedge clk) quadB_delayed1 <= {quadB_delayed1[1:0], quadB[1]}; always @(posedge clk) quadA_delayed2 <= {quadA_delayed2[1:0], quadA[2]}; always @(posedge clk) quadB_delayed2 <= {quadB_delayed2[1:0], quadB[2]}; always @(posedge clk) quadA_delayed3 <= {quadA_delayed3[1:0], quadA[3]}; always @(posedge clk) quadB_delayed3 <= {quadB_delayed3[1:0], quadB[3]}; always @(posedge clk) quadA_delayed4 <= {quadA_delayed4[1:0], quadA[4]}; always @(posedge clk) quadB_delayed4 <= {quadB_delayed4[1:0], quadB[4]}; /*********************************************************************************************************/ wire count_enable0 = quadA_delayed0[1] ^ quadA_delayed0[2] ^ quadB_delayed0[1] ^ quadB_delayed0[2]; wire count_direction0 = quadA_delayed0[1] ^ quadB_delayed0[2]; wire count_enable1 = quadA_delayed1[1] ^ quadA_delayed1[2] ^ quadB_delayed1[1] ^ quadB_delayed1[2]; wire count_direction1 = quadA_delayed1[1] ^ quadB_delayed1[2]; wire count_enable2 = quadA_delayed2[1] ^ quadA_delayed2[2] ^ quadB_delayed2[1] ^ quadB_delayed2[2]; wire count_direction2 = quadA_delayed2[1] ^ quadB_delayed2[2]; wire count_enable3 = quadA_delayed3[1] ^ quadA_delayed3[2] ^ quadB_delayed3[1] ^ quadB_delayed3[2]; wire count_direction3 = quadA_delayed3[1] ^ quadB_delayed3[2]; wire count_enable4 = quadA_delayed4[1] ^ quadA_delayed4[2] ^ quadB_delayed4[1] ^ quadB_delayed4[2]; wire count_direction4 = quadA_delayed4[1] ^ quadB_delayed4[2]; /*********************************************************************************************************/ reg [15:0] count_buf0; reg [15:0] count_buf1; reg [15:0] count_buf2; reg [15:0] count_buf3; reg [15:0] count_buf4; //reg [15:0] count_buf5; //reg [15:0] count_buf6; /*********************************************************************************************************/ always @(posedge clk) begin if(count_enable0) begin if(count_direction0) count_buf0<=count_buf0+8'b0000_0001; else count_buf0<=count_buf0-8'b0000_0001; end end /*********************************************************************************************************/ always @(posedge clk) begin if(count_enable1) begin if(count_direction1) count_buf1<=count_buf1+8'b0000_0001; else count_buf1<=count_buf1-8'b0000_0001; end end /*********************************************************************************************************/ always @(posedge clk) begin if(count_enable2) begin if(count_direction2) count_buf2<=count_buf2+8'b0000_0001; else count_buf2<=count_buf2-8'b0000_0001; end end /*********************************************************************************************************/ always @(posedge clk) begin if(count_enable3) begin if(count_direction3) count_buf3<=count_buf3+8'b0000_0001; else count_buf3<=count_buf3-8'b0000_0001; end end /*********************************************************************************************************/ always @(posedge clk) begin if(count_enable4) begin if(count_direction4) count_buf4<=count_buf4+8'b0000_0001; else count_buf4<=count_buf4-8'b0000_0001; end end /*********************************************************************************************************/ //dispose the switch value /*********************************************************************************************************/ // First use two flipflops to synchronize the PB signal the "clk" clock domain /*********************************************************************************************************/ //PB0 reg PB0_sync_0; always @(posedge clk) PB0_sync_0 <= ~PB[0]; // invert PB to make PB_sync_0 active high reg PB0_sync_1; always @(posedge clk) PB0_sync_1 <= PB0_sync_0; /*********************************************************************************************************/ //PB1 reg PB1_sync_0; always @(posedge clk) PB1_sync_0 <= ~PB[1]; // invert PB to make PB_sync_0 active high reg PB1_sync_1; always @(posedge clk) PB1_sync_1 <= PB1_sync_0; /*********************************************************************************************************/ //PB2 reg PB2_sync_0; always @(posedge clk) PB2_sync_0 <= ~PB[2]; // invert PB to make PB_sync_0 active high reg PB2_sync_1; always @(posedge clk) PB2_sync_1 <= PB2_sync_0; /*********************************************************************************************************/ //PB3 reg PB3_sync_0; always @(posedge clk) PB3_sync_0 <= ~PB[3]; // invert PB to make PB_sync_0 active high reg PB3_sync_1; always @(posedge clk) PB3_sync_1 <= PB3_sync_0; /*********************************************************************************************************/ //PB4 reg PB4_sync_0; always @(posedge clk) PB4_sync_0 <= ~PB[4]; // invert PB to make PB_sync_0 active high reg PB4_sync_1; always @(posedge clk) PB4_sync_1 <= PB4_sync_0; /*********************************************************************************************************/ //PB5 reg PB5_sync_0; always @(posedge clk) PB5_sync_0 <= ~PB[5]; // invert PB to make PB_sync_0 active high reg PB5_sync_1; always @(posedge clk) PB5_sync_1 <= PB5_sync_0; /*********************************************************************************************************/ //PB6 reg PB6_sync_0; always @(posedge clk) PB6_sync_0 <= ~PB[6]; // invert PB to make PB_sync_0 active high reg PB6_sync_1; always @(posedge clk) PB6_sync_1 <= PB6_sync_0; /*********************************************************************************************************/ //PB7 reg PB7_sync_0; always @(posedge clk) PB7_sync_0 <= ~PB[7]; // invert PB to make PB_sync_0 active high reg PB7_sync_1; always @(posedge clk) PB7_sync_1 <= PB7_sync_0; /*********************************************************************************************************/ //PB8 reg PB8_sync_0; always @(posedge clk) PB8_sync_0 <= ~PB[8]; // invert PB to make PB_sync_0 active high reg PB8_sync_1; always @(posedge clk) PB8_sync_1 <= PB8_sync_0; /*********************************************************************************************************/ //PB9 reg PB9_sync_0; always @(posedge clk) PB9_sync_0 <= ~PB[9]; // invert PB to make PB_sync_0 active high reg PB9_sync_1; always @(posedge clk) PB9_sync_1 <= PB9_sync_0; /*********************************************************************************************************/ //PB10 reg PB10_sync_0; always @(posedge clk) PB10_sync_0 <= ~PB[10]; // invert PB to make PB_sync_0 active high reg PB10_sync_1; always @(posedge clk) PB10_sync_1 <= PB10_sync_0; /*********************************************************************************************************/ //PB11 reg PB11_sync_0; always @(posedge clk) PB11_sync_0 <= ~PB[11]; // invert PB to make PB_sync_0 active high reg PB11_sync_1; always @(posedge clk) PB11_sync_1 <= PB11_sync_0; /*********************************************************************************************************/ //PB12 reg PB12_sync_0; always @(posedge clk) PB12_sync_0 <= ~PB[12]; // invert PB to make PB_sync_0 active high reg PB12_sync_1; always @(posedge clk) PB12_sync_1 <= PB12_sync_0; /*********************************************************************************************************/ //PB13 reg PB13_sync_0; always @(posedge clk) PB13_sync_0 <= ~PB[13]; // invert PB to make PB_sync_0 active high reg PB13_sync_1; always @(posedge clk) PB13_sync_1 <= PB13_sync_0; /*********************************************************************************************************/ //PB14 reg PB14_sync_0; always @(posedge clk) PB14_sync_0 <= ~PB[14]; // invert PB to make PB_sync_0 active high reg PB14_sync_1; always @(posedge clk) PB14_sync_1 <= PB14_sync_0; /*********************************************************************************************************/ //PB15 reg PB15_sync_0; always @(posedge clk) PB15_sync_0 <= ~PB[15]; // invert PB to make PB_sync_0 active high reg PB15_sync_1; always @(posedge clk) PB15_sync_1 <= PB15_sync_0; /*********************************************************************************************************/ //PB16 reg PB16_sync_0; always @(posedge clk) PB16_sync_0 <= ~PB[16]; // invert PB to make PB_sync_0 active high reg PB16_sync_1; always @(posedge clk) PB16_sync_1 <= PB16_sync_0; /*********************************************************************************************************/ //PB17 reg PB17_sync_0; always @(posedge clk) PB17_sync_0 <= ~PB[17]; // invert PB to make PB_sync_0 active high reg PB17_sync_1; always @(posedge clk) PB17_sync_1 <= PB17_sync_0; /*********************************************************************************************************/ //PB18 reg PB18_sync_0; always @(posedge clk) PB18_sync_0 <= ~PB[18]; // invert PB to make PB_sync_0 active high reg PB18_sync_1; always @(posedge clk) PB18_sync_1 <= PB18_sync_0; /*********************************************************************************************************/ //PB19 reg PB19_sync_0; always @(posedge clk) PB19_sync_0 <= ~PB[19]; // invert PB to make PB_sync_0 active high reg PB19_sync_1; always @(posedge clk) PB19_sync_1 <= PB19_sync_0; /*********************************************************************************************************/ //PB20 reg PB20_sync_0; always @(posedge clk) PB20_sync_0 <= ~PB[20]; // invert PB to make PB_sync_0 active high reg PB20_sync_1; always @(posedge clk) PB20_sync_1 <= PB20_sync_0; /*********************************************************************************************************/ //PB21 reg PB21_sync_0; always @(posedge clk) PB21_sync_0 <= ~PB[21]; // invert PB to make PB_sync_0 active high reg PB21_sync_1; always @(posedge clk) PB21_sync_1 <= PB21_sync_0; /*********************************************************************************************************/ //PB22 reg PB22_sync_0; always @(posedge clk) PB22_sync_0 <= ~PB[22]; // invert PB to make PB_sync_0 active high reg PB22_sync_1; always @(posedge clk) PB22_sync_1 <= PB22_sync_0; /*********************************************************************************************************/ //PB23 reg PB23_sync_0; always @(posedge clk) PB23_sync_0 <= ~PB[23]; // invert PB to make PB_sync_0 active high reg PB23_sync_1; always @(posedge clk) PB23_sync_1 <= PB23_sync_0; /*********************************************************************************************************/ // Next declare 24 17-bits counters reg [16:0] PB0_cnt, PB1_cnt, PB2_cnt, PB3_cnt, PB4_cnt, PB5_cnt, PB6_cnt, PB7_cnt, PB8_cnt, PB9_cnt; reg [16:0] PB10_cnt, PB11_cnt, PB12_cnt, PB13_cnt, PB14_cnt, PB15_cnt, PB16_cnt, PB17_cnt, PB18_cnt, PB19_cnt; reg [16:0] PB20_cnt, PB21_cnt, PB22_cnt, PB23_cnt; // When the push-button is pushed or released, we increment the counter // The counter has to be maxed out before we decide that the push-button state has changed reg [23:0] PB_state; // state of the push-button (0 when up, 1 when down) /*********************************************************************************************************/ //PB0 wire PB0_idle = (PB_state[0]==PB0_sync_1); wire PB0_cnt_max = &PB0_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB0_idle) PB0_cnt <= 0; // nothing's going on else begin PB0_cnt <= PB0_cnt + 1; // something's going on, increment the counter if(PB0_cnt_max) PB_state[0] <= ~PB_state[0]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB1 wire PB1_idle = (PB_state[1]==PB1_sync_1); wire PB1_cnt_max = &PB1_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB1_idle) PB1_cnt <= 0; // nothing's going on else begin PB1_cnt <= PB1_cnt + 1; // something's going on, increment the counter if(PB1_cnt_max) PB_state[1] <= ~PB_state[1]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB2 wire PB2_idle = (PB_state[2]==PB2_sync_1); wire PB2_cnt_max = &PB2_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB2_idle) PB2_cnt <= 0; // nothing's going on else begin PB2_cnt <= PB2_cnt + 1; // something's going on, increment the counter if(PB2_cnt_max) PB_state[2] <= ~PB_state[2]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB3 wire PB3_idle = (PB_state[3]==PB3_sync_1); wire PB3_cnt_max = &PB3_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB3_idle) PB3_cnt <= 0; // nothing's going on else begin PB3_cnt <= PB3_cnt + 1; // something's going on, increment the counter if(PB3_cnt_max) PB_state[3] <= ~PB_state[3]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB4 wire PB4_idle = (PB_state[4]==PB4_sync_1); wire PB4_cnt_max = &PB4_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB4_idle) PB4_cnt <= 0; // nothing's going on else begin PB4_cnt <= PB4_cnt + 1; // something's going on, increment the counter if(PB4_cnt_max) PB_state[4] <= ~PB_state[4]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB5 wire PB5_idle = (PB_state[5]==PB5_sync_1); wire PB5_cnt_max = &PB5_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB5_idle) PB5_cnt <= 0; // nothing's going on else begin PB5_cnt <= PB5_cnt + 1; // something's going on, increment the counter if(PB5_cnt_max) PB_state[5] <= ~PB_state[5]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB6 wire PB6_idle = (PB_state[6]==PB6_sync_1); wire PB6_cnt_max = &PB6_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB6_idle) PB6_cnt <= 0; // nothing's going on else begin PB6_cnt <= PB6_cnt + 1; // something's going on, increment the counter if(PB6_cnt_max) PB_state[6] <= ~PB_state[6]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB7 wire PB7_idle = (PB_state[7]==PB7_sync_1); wire PB7_cnt_max = &PB7_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB7_idle) PB7_cnt <= 0; // nothing's going on else begin PB7_cnt <= PB7_cnt + 1; // something's going on, increment the counter if(PB7_cnt_max) PB_state[7] <= ~PB_state[7]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB8 wire PB8_idle = (PB_state[8]==PB8_sync_1); wire PB8_cnt_max = &PB8_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB8_idle) PB8_cnt <= 0; // nothing's going on else begin PB8_cnt <= PB8_cnt + 1; // something's going on, increment the counter if(PB8_cnt_max) PB_state[8] <= ~PB_state[8]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB9 wire PB9_idle = (PB_state[9]==PB9_sync_1); wire PB9_cnt_max = &PB9_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB9_idle) PB9_cnt <= 0; // nothing's going on else begin PB9_cnt <= PB9_cnt + 1; // something's going on, increment the counter if(PB9_cnt_max) PB_state[9] <= ~PB_state[9]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB10 wire PB10_idle = (PB_state[10]==PB10_sync_1); wire PB10_cnt_max = &PB10_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB10_idle) PB10_cnt <= 0; // nothing's going on else begin PB10_cnt <= PB10_cnt + 1; // something's going on, increment the counter if(PB10_cnt_max) PB_state[10] <= ~PB_state[10]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB11 wire PB11_idle = (PB_state[11]==PB11_sync_1); wire PB11_cnt_max = &PB11_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB11_idle) PB11_cnt <= 0; // nothing's going on else begin PB11_cnt <= PB11_cnt + 1; // something's going on, increment the counter if(PB11_cnt_max) PB_state[11] <= ~PB_state[11]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB12 wire PB12_idle = (PB_state[12]==PB12_sync_1); wire PB12_cnt_max = &PB12_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB12_idle) PB12_cnt <= 0; // nothing's going on else begin PB12_cnt <= PB12_cnt + 1; // something's going on, increment the counter if(PB12_cnt_max) PB_state[12] <= ~PB_state[12]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB13 wire PB13_idle = (PB_state[13]==PB13_sync_1); wire PB13_cnt_max = &PB13_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB13_idle) PB13_cnt <= 0; // nothing's going on else begin PB13_cnt <= PB13_cnt + 1; // something's going on, increment the counter if(PB13_cnt_max) PB_state[13] <= ~PB_state[13]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB14 wire PB14_idle = (PB_state[14]==PB14_sync_1); wire PB14_cnt_max = &PB14_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB14_idle) PB14_cnt <= 0; // nothing's going on else begin PB14_cnt <= PB14_cnt + 1; // something's going on, increment the counter if(PB14_cnt_max) PB_state[14] <= ~PB_state[14]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB15 wire PB15_idle = (PB_state[15]==PB15_sync_1); wire PB15_cnt_max = &PB15_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB15_idle) PB15_cnt <= 0; // nothing's going on else begin PB15_cnt <= PB15_cnt + 1; // something's going on, increment the counter if(PB15_cnt_max) PB_state[15] <= ~PB_state[15]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB16 wire PB16_idle = (PB_state[16]==PB16_sync_1); wire PB16_cnt_max = &PB16_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB16_idle) PB16_cnt <= 0; // nothing's going on else begin PB16_cnt <= PB16_cnt + 1; // something's going on, increment the counter if(PB16_cnt_max) PB_state[16] <= ~PB_state[16]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB17 wire PB17_idle = (PB_state[17]==PB17_sync_1); wire PB17_cnt_max = &PB17_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB17_idle) PB17_cnt <= 0; // nothing's going on else begin PB17_cnt <= PB17_cnt + 1; // something's going on, increment the counter if(PB17_cnt_max) PB_state[17] <= ~PB_state[17]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB18 wire PB18_idle = (PB_state[18]==PB18_sync_1); wire PB18_cnt_max = &PB18_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB18_idle) PB18_cnt <= 0; // nothing's going on else begin PB18_cnt <= PB18_cnt + 1; // something's going on, increment the counter if(PB18_cnt_max) PB_state[18] <= ~PB_state[18]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB19 wire PB19_idle = (PB_state[19]==PB19_sync_1); wire PB19_cnt_max = &PB19_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB19_idle) PB19_cnt <= 0; // nothing's going on else begin PB19_cnt <= PB19_cnt + 1; // something's going on, increment the counter if(PB19_cnt_max) PB_state[19] <= ~PB_state[19]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB20 wire PB20_idle = (PB_state[20]==PB20_sync_1); wire PB20_cnt_max = &PB20_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB20_idle) PB20_cnt <= 0; // nothing's going on else begin PB20_cnt <= PB20_cnt + 1; // something's going on, increment the counter if(PB20_cnt_max) PB_state[20] <= ~PB_state[20]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB21 wire PB21_idle = (PB_state[21]==PB21_sync_1); wire PB21_cnt_max = &PB21_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB21_idle) PB21_cnt <= 0; // nothing's going on else begin PB21_cnt <= PB21_cnt + 1; // something's going on, increment the counter if(PB21_cnt_max) PB_state[21] <= ~PB_state[21]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB22 wire PB22_idle = (PB_state[22]==PB22_sync_1); wire PB22_cnt_max = &PB22_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB22_idle) PB22_cnt <= 0; // nothing's going on else begin PB22_cnt <= PB22_cnt + 1; // something's going on, increment the counter if(PB22_cnt_max) PB_state[22] <= ~PB_state[22]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //PB23 wire PB23_idle = (PB_state[23]==PB23_sync_1); wire PB23_cnt_max = &PB23_cnt; // true when all bits of PB_cnt are 1's always @(posedge clk) begin if(PB23_idle) PB23_cnt <= 0; // nothing's going on else begin PB23_cnt <= PB23_cnt + 1; // something's going on, increment the counter if(PB23_cnt_max) PB_state[23] <= ~PB_state[23]; // if the counter is maxed out, PB changed! end end /*********************************************************************************************************/ //wire PB_down = ~PB_state & ~PB_idle & PB_cnt_max; // true for one clock cycle when we detect that PB went down //wire PB_up = PB_state & ~PB_idle & PB_cnt_max; // true for one clock cycle when we detect that PB went up /*********************************************************************************************************/ //assign count_buf5=PB_state[15:0]; //assign count_buf6={8'b0, PB_state[23:16]}; reg [15:0] count_buf; always @(posedge clk) begin case (condition) 3'b000: count_buf <= count_buf0; 3'b001: count_buf <= count_buf1; 3'b010: count_buf <= count_buf2; 3'b011: count_buf <= count_buf3; 3'b100: count_buf <= count_buf4; 3'b101: count_buf <= PB_state[15:0]; 3'b110: count_buf <= PB_state[23:16]; endcase end assign count=count_buf; endmodule /********************************************************************************************************* * Two channels Decodre_Input which is Tested successful by tiger ********************************************************************************************************** module decoder_test(clk, condition, quadA, quadB, count); input clk; input [1:0] quadA, quadB; input [1:0] condition; output [7:0] count; reg [2:0] quadA_delayed0; reg [2:0] quadB_delayed0; reg [2:0] quadA_delayed1; reg [2:0] quadB_delayed1; always @(posedge clk) quadA_delayed0 <= {quadA_delayed0[1:0], quadA[0]}; always @(posedge clk) quadB_delayed0 <= {quadB_delayed0[1:0], quadB[0]}; always @(posedge clk) quadA_delayed1 <= {quadA_delayed1[1:0], quadA[1]}; always @(posedge clk) quadB_delayed1 <= {quadB_delayed1[1:0], quadB[1]}; wire count_enable0 = quadA_delayed0[1] ^ quadA_delayed0[2] ^ quadB_delayed0[1] ^ quadB_delayed0[2]; wire count_direction0 = quadA_delayed0[1] ^ quadB_delayed0[2]; wire count_enable1 = quadA_delayed1[1] ^ quadA_delayed1[2] ^ quadB_delayed1[1] ^ quadB_delayed1[2]; wire count_direction1 = quadA_delayed1[1] ^ quadB_delayed1[2]; reg [7:0] count_buf0; reg [7:0] count_buf1; always @(posedge clk) begin if(count_enable0) begin if(count_direction0) count_buf0<=count_buf0+1; else count_buf0<=count_buf0-1; end end always @(posedge clk) begin if(count_enable1) begin if(count_direction1) count_buf1<=count_buf1+1; else count_buf1<=count_buf1-1; end end reg [15:0] count_buf; always @(posedge clk) begin case (condition) 2'b00: count_buf <= count_buf0; 2'b11: count_buf <= count_buf1; endcase end assign count=count_buf; endmodule *********************************************************************************************************/