sampling_moudle‘s V files(with 24 Keys, 5 Decoders)

最新推荐文章于 2023-06-06 15:28:56 发布

xmjulytiger

最新推荐文章于 2023-06-06 15:28:56 发布

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分类专栏： Verilog HDL 文章标签： asynchronous signal module input domain output

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module Decoder0
(
	clk, RSTn, quadA, quadB, count
);

/************************************************************************************************/

input clk, RSTn, quadA, quadB;
output [15:0] count;			//Decoder0 for steering wheel, so use 16 bits to count

/************************************************************************************************/

reg [2:0] quadA_delayed, quadB_delayed;

always @(posedge clk) quadA_delayed <= {quadA_delayed[1:0], quadA};
always @(posedge clk) quadB_delayed <= {quadB_delayed[1:0], quadB};

wire count_enable = quadA_delayed[1] ^ quadA_delayed[2] ^ quadB_delayed[1] ^ quadB_delayed[2];
wire count_direction = quadA_delayed[1] ^ quadB_delayed[2];

/************************************************************************************************/

reg [15:0] count;

always @(posedge clk or negedge RSTn)
	if(!RSTn)
		count<=16'd0;
	else	
		begin
			if(count_enable)
				begin
					if(count_direction) count<=count+16'b1; else count<=count-16'b1;
				end
		end

/************************************************************************************************/

endmodule

module Decoder_Out
(
	clk, RSTn, quadA, quadB, count_Out
);

/*****************************************/

input clk, RSTn;
input [4:0] quadA, quadB;
output [47:0] count_Out;

/*****************************************/

wire [15:0] count0;

Decoder0 U1
(
	.clk(clk),
	.RSTn(RSTn),
	.quadA(quadA[0]),
	.quadB(quadB[0]),
	.count(count0)
);	

/*****************************************/

wire [7:0] count1;

Decoder1 U2
(
	.clk(clk),
	.RSTn(RSTn),
	.quadA(quadA[1]),
	.quadB(quadB[1]),
	.count(count1)
);	

/*****************************************/

wire [7:0] count2;

Decoder2 U3
(
	.clk(clk),
	.RSTn(RSTn),
	.quadA(quadA[2]),
	.quadB(quadB[2]),
	.count(count2)
);	

/*****************************************/

wire [7:0] count3;

Decoder3 U4
(
	.clk(clk),
	.RSTn(RSTn),
	.quadA(quadA[3]),
	.quadB(quadB[3]),
	.count(count3)
);	

/*****************************************/

wire [7:0] count4;

Decoder4 U5
(
	.clk(clk),
	.RSTn(RSTn),
	.quadA(quadA[4]),
	.quadB(quadB[4]),
	.count(count4)
);	

/**********************************************************/

assign count_Out={count4, count3, count2, count1, count0};

/**********************************************************/

endmodule

module Key0
(  
        clk, RSTn, Key_In, Key_Out  
);

/************************************************************************************************************/
  
input clk, RSTn;  // "clk" is the clock  
input Key_In;  // "Key_In" is the glitched, asynchronous, active low push-button signal  
output Key_Out;  // 1 while the push-button is active (down)  

/************************************************************************************************************/
 
// First use two flipflops to synchronize the Key signal the "clk" clock domain 
 
reg Key_sync_0;  always @(posedge clk) Key_sync_0 <= ~Key_In;  // invert Key_In to make Key_sync_0 active high  
reg Key_sync_1;  always @(posedge clk) Key_sync_1 <= Key_sync_0;
  
// Next declare a 16-bits counter 
 
reg [17:0] Key_cnt;  

// When the push-button is pushed or released, we increment the counter  
// The counter has to be maxed out before we decide that the push-button state has changed  

reg Key_Out;  // state of the push-button (0 when up, 1 when down) 
 
wire Key_idle = (Key_Out==Key_sync_1);  
wire Key_cnt_max = &Key_cnt;    // true when all bits of Key_cnt are 1's  

/************************************************************************************************************/

always @(posedge clk or negedge RSTn)  
        if(!RSTn)  
                Key_cnt <= 16'd0;  
                                  
        else if(Key_idle)  
            Key_cnt <=16'd0;  // nothing's going on  
              
        else  
                begin  
                    Key_cnt <= Key_cnt + 18'b1;  // something's going on, increment the counter  
                    if(Key_cnt_max) Key_Out <= ~Key_Out;  // if the counter is maxed out, Key_Out changed!  
                end
                
/************************************************************************************************************/
                  
endmodule

module Key_Out  
(  
	clk, RSTn, Key_In, Key_out  
);  

/***************************************/

input clk, RSTn;
input [23:0] Key_In;
output [23:0] Key_out;  

/***************************************/
 
wire Key0_Out;  
Key0 U1   
(  
	.clk(clk),  
    .RSTn(RSTn), 
    .Key_In(Key_In[0]),
    .Key_Out(Key0_Out)  
); 
  
/***************************************/

wire Key1_Out;  
Key1 U2  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[1]),  
    .Key_Out(Key1_Out)  
); 
  
/***************************************/  

wire Key2_Out;  
Key2 U3  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[2]),  
    .Key_Out(Key2_Out)  
); 
  
/***************************************/  

wire Key3_Out;  
Key3 U4  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[3]),  
    .Key_Out(Key3_Out)  
); 
  
/***************************************/  

wire Key4_Out;  
Key4 U5  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[4]),  
    .Key_Out(Key4_Out)  
); 
  
/***************************************/  

wire Key5_Out;  
Key5 U6  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[5]),  
    .Key_Out(Key5_Out)  
); 
  
/***************************************/  

wire Key6_Out;  
Key6 U7  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[6]),  
    .Key_Out(Key6_Out)  
); 
  
/***************************************/  

wire Key7_Out;  
Key7 U8  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[7]),  
    .Key_Out(Key7_Out)  
); 
  
/***************************************/  

wire Key8_Out;  
Key8 U9  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[8]),  
    .Key_Out(Key8_Out)  
); 
  
/***************************************/  

wire Key9_Out;  
Key9 U10  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[9]),  
    .Key_Out(Key9_Out)  
); 
  
/***************************************/  

wire Key10_Out;  
Key10 U11  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[10]),  
    .Key_Out(Key10_Out)  
); 
  
/***************************************/  

wire Key11_Out;  
Key11 U12  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[11]),  
    .Key_Out(Key11_Out)  
); 
  
/***************************************/  

wire Key12_Out;  
Key12 U13  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[12]),  
    .Key_Out(Key12_Out)  
); 
  
/***************************************/  

wire Key13_Out;  
Key13 U14  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[13]),  
    .Key_Out(Key13_Out)  
); 
  
/***************************************/  

wire Key14_Out;  
Key14 U15  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[14]),  
    .Key_Out(Key14_Out)  
); 
  
/***************************************/  

wire Key15_Out;  
Key15 U16  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[15]),  
    .Key_Out(Key15_Out)  
); 
  
/***************************************/  

wire Key16_Out;  
Key16 U17  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[16]),  
    .Key_Out(Key16_Out)  
); 
  
/***************************************/ 


wire Key17_Out;  
Key17 U18  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[17]),  
    .Key_Out(Key17_Out)  
); 
  
/***************************************/   

wire Key18_Out;  
Key18 U19  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[18]),  
    .Key_Out(Key18_Out)  
); 
  
/***************************************/  

wire Key19_Out;  
Key19 U20  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[19]),  
    .Key_Out(Key19_Out)  
); 
  
/***************************************/  

wire Key20_Out;  
Key20 U21  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[20]),  
    .Key_Out(Key20_Out)  
); 
  
/***************************************/  

wire Key21_Out;  
Key21 U22  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[21]),  
    .Key_Out(Key21_Out)  
); 
  
/***************************************/  

wire Key22_Out;  
Key22 U23  
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[22]),  
    .Key_Out(Key22_Out)  
); 
  
/***************************************/  

wire Key23_Out;  
Key23 U24 
(  
    .clk(clk),  
    .RSTn(RSTn),
    .Key_In(Key_In[23]),  
    .Key_Out(Key23_Out)  
);
  
/***************************************/  

assign Key_out={
					Key23_Out, Key22_Out,
					Key21_Out, Key20_Out,
					Key19_Out, Key18_Out,
					Key17_Out, Key16_Out,
					Key15_Out, Key14_Out,
					Key13_Out, Key12_Out,
					Key11_Out, Key10_Out,
					Key9_Out, Key8_Out,
					Key7_Out, Key6_Out,
					Key5_Out, Key4_Out,
					Key3_Out, Key2_Out, 
					Key1_Out, Key0_Out
				}; 
 
/***************************************/

endmodule

module Sampling_moudle
(
	clk, RSTn, 
	Read_count_Out, Read_Key_Out,
	Data_Out
);

/*********************************************/

input clk, RSTn;
input [23:0] Read_Key_Out;
input [47:0] Read_count_Out;

output[7:0] Data_Out;

/*********************************************/

Key_Out U1
(
	.clk(clk),
	.RSTn(RSTn),
	.Key_out(Read_Key_out)	
);

/*********************************************/

Decoder_Out U2
(
	.clk(clk),
	.RSTn(RSTn),
	.count_Out(Read_count_out)	
);

/*********************************************/

endmodule