module Decoder0 ( clk, RSTn, quadA, quadB, count ); input clk, RSTn, quadA, quadB; output [7:0] count; reg [2:0] quadA_delayed, quadB_delayed; always @(posedge clk) quadA_delayed <= {quadA_delayed[1:0], quadA}; always @(posedge clk) quadB_delayed <= {quadB_delayed[1:0], quadB}; wire count_enable = quadA_delayed[1] ^ quadA_delayed[2] ^ quadB_delayed[1] ^ quadB_delayed[2]; wire count_direction = quadA_delayed[1] ^ quadB_delayed[2]; reg [7:0] count; always @(posedge clk or negedge RSTn) if(!RSTn) count<=8'd0; else begin if(count_enable) begin if(count_direction) count<=count+8'd1; else count<=count-8'd1; end end endmodule module Decoder1 ( clk, RSTn, quadA, quadB, count ); input clk, RSTn, quadA, quadB; output [7:0] count; reg [2:0] quadA_delayed, quadB_delayed; always @(posedge clk) quadA_delayed <= {quadA_delayed[1:0], quadA}; always @(posedge clk) quadB_delayed <= {quadB_delayed[1:0], quadB}; wire count_enable = quadA_delayed[1] ^ quadA_delayed[2] ^ quadB_delayed[1] ^ quadB_delayed[2]; wire count_direction = quadA_delayed[1] ^ quadB_delayed[2]; reg [7:0] count; always @(posedge clk or negedge RSTn) if(!RSTn) count<=8'd0; else begin if(count_enable) begin if(count_direction) count<=count+8'd1; else count<=count-8'd1; end end endmodule module Decoder_Out ( clk, RSTn, quadA, quadB, count_Out ); /*****************************************/ input clk, RSTn; input [1:0] quadA, quadB; output [15:0] count_Out; /*****************************************/ wire [7:0] count0; Decoder0 U1 ( .clk(clk), .RSTn(RSTn), .quadA(quadA[0]), .quadB(quadB[0]), .count(count0) ); /*****************************************/ wire [7:0] count1; Decoder1 U2 ( .clk(clk), .RSTn(RSTn), .quadA(quadA[1]), .quadB(quadB[1]), .count(count1) ); /*****************************************/ assign count_Out={count1, count0}; /*****************************************/ endmodule