GlueLogic : TOP层只有连线,与门就是一个gluelogic
TOP层
module ahb_calc_top(
//input singals
hclk,
hresetn,
hsel,
hwrite,
hready,
hsize,
htrans,
hburst,
hwdata,
haddr,
//output singals
hresp,
hready_resp,
hrdata
);
input hclk;
input hresetn;
input hsel;
input hwrite;
input hready;
input [2:0] hsize;
input [1:0] htrans;
input [2:0] hburst;
input [31:0] hwdata;
input [31:0] haddr;
output hready_resp;
output[1:0] hresp;
output[31:0] hrdata;
wire ctrl;
wire [1:0] calc_mode;
wire [15:0] opcode_a;
wire [15:0] opcode_b;
wire [31:0] result;
ahb_slave_calc U_slave_if(
.hclk (hclk ),
.hresetn (hresetn ),
.hsel (hsel ),
.hwrite (hwrite ),
.hready (hready ),
.hsize (hsize ),
.htrans (htrans ),
.hburst (hburst ),
.hwdata (hwdata ),
.haddr (haddr ),
.result (result ),
.hready (hready ),
.hready_resp (hready_resp),
.hresp (hresp ),
.hrdata (hrdata ),
.ctrl (ctrl ),
.calc_mode (calc_mode ),
.opcode_a (opcode_a ),
.opcode_b (opcode_b )
);
calc U_calc(
.ctrl (ctrl ),
.calc_mode (calc_mode ),
.opcode_a (opcode_a ),
.opcode_b (opcode_b ),
.result (result )
);
endmodule
Slave
module ahb_slave_calc(
//input signals
hclk,
hresetn,
hsel,
hwrite,
hready,
hsize,
htrans,
hburst,
hwdata,
haddr,
result,
//output signal
hready_resp,
hresp,
hrdata,
ctrl,
calc_mode,
opcode_a,
opcode_b
);
//two response,one is of bus read and write response,the other is hready response to gvie bus
input hclk;
input hresetn;
input hsel;
input hwrite;
input hready;
input [2:0] hsize;
input [1:0] htrans;
input [2:0] hburst;
input [31:0] hwdata;
input [31:0] haddr;
input [31:0] result;
output hready_resp;
output[1:0] hresp