5.1.8.1 PF PCI Power Management Capability Register Details
Core实现了power management Capability,该capability默认情况下是基本配置空间的数据链表中的第一个capability。以下是与power management实现的模块:
Ø Power Managementregister space
Ø Link state information(provided to both the application logic and PHY interfaces)
Ø Power management-readyclock and reset implementation
下面的章节描述的是register的相关内容,而其他两个部分可以通过查阅通过PCI PowerManagement specification and the PCI Express 3.0 Specification获得更加详细的内容。
Table 5-61 PF Power Management Capability Structure
Byte Offset |
Byte 3 |
Byte 2 |
Byte 1 |
Byte 0 |
|
Power Management Capabilities (PMC)(RO(cs)) |