常用关键字
关键字 | 含义 |
module | 模块开始定义 |
input | 输入端口定义 |
output | 输出端口定义 |
inout | 双向端口定义 |
parameter | 信号的参数定义 |
wire | wire信号定义 |
reg | reg信号定义 |
always | 产生reg信号语句的关键字 |
assign | 产生wire信号语句的关键字 |
begin | 语句的起始标志 |
end | 语句的结束标志 |
posedge/negedge | 时序电路的标志 |
case | Case语句起始标记 |
default | Case语句的默认分支标志 |
endcase | Case语句结束标记 |
if | if/else语句标记 |
else | if/else语句标记 |
for | for语句标记 |
endmodule | 模块结束定义 |
Verilog所有关键字
and | always | assign | begin | buf |
bufif0 | bufif1 | case | casex | casez |
cmos | deassign | default | defparam | disable |
edge | else | end | endcase | endfunction |
endprimitive | endmodule | endspecify | endtable | endtask |
event | for | force | forever | fork |
function | highz0 | highz1 | if | ifnone |
initial | inout | input | integer | join |
large | macromodule | medium | module | nand |
negedge | nor | not | notif0 | notif1 |
nmos | or | output | parameter | pmos |
posedge | primitive | pulldown | pullup | pull0 |
pull1 | rcmos | real | realtime | reg |
release | repeat | rnmos | rpmos | rtran |
rtranif0 | rtranif1 | scalared | small | specify |
specparam | strength | strong0 | strong1 | supply0 |
supply1 | table | task | tran | tranif0 |
tranif1 | time | tri | triand | trior |
trireg | tri0 | tri1 | vectored | wait |
wand | weak0 | weak1 | while | wire |
wor | xnor | xor |