附录B：Standard Delay Format(SDF)(下)

---

---

B.4 映射实例(Mapping Examples)

以下是将$SDF$结构映射到$VHDL$泛型（generic）和$VerilogHDL$声明（declaration）的示例。

传播延迟(Propagation Delay)

• 从输入端口$A$到输出端口$Y$的传播延迟：上升时间为$0.406$，下降时间为$0.339$：

// SDF:
(IOPATH A Y (0.406) (0.339))

-- VHDL generic:
tpd_A_Y : VitalDelayType01;

// Verilog HDL specify path:
(A *> Y) = (tplh$A$Y, tphl$A$Y);

• 从输入端口$OE$到输出端口$Y$的传播延迟：上升时间为$0.441$，下降时间为$0.409$。最小、标准和最大延迟是相同的：

// SDF:
(IOPATH OE Y (0.441:0.441:0.441) (0.409:0.409:0.409))

-- VHDL generic:
tpd_OE_Y : VitalDelayType01Z;

// Verilog HDL specify path:
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);

• 从输入端口$S0$到输出端口$Y$的条件传播延迟：

// SDF:
(COND A==0 && B==1 && S1==0
	(IOPATH S0 Y (0.062:0.062:0.062) (0.048:0.048:0.048)
	)
)

-- VHDL generic:
tpd_S0_Y_A_EQ_0_AN_B_EQ_1_AN_S1_EQ_0 :
	VitalDelayType01;
	
// Verilog HDL specify path:
if ((A == 1'b0) && (B == 1'b1) && (S1 == 1'b0))
	(S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);

• 从输入端口$A$到输出端口$Y$的条件传播延迟：

// SDF:
(COND B == 0
	(IOPATH A Y (0.130) (0.098)
	)
)

-- VHDL generic:
tpd_A_Y_B_EQ_0 : VitalDelayType01;

// Verilog HDL specify path:
if (B == 1'b0)
	(A *> Y) = 0;

• 从输入端口$CK$到输出端口$Q$的传播延迟：

// SDF:
(IOPATH CK Q (0.100:0.100:0.100) (0.118:0.118:0.118))

-- VHDL generic:
tpd_CK_Q : VitalDelayType01;

// Verilog HDL specify path:
(CK *> Q) = (tplh$CK$Q, tphl$CK$Q);

• 从输入端口$A$到输出端口$Y$的条件传播延迟：

// SDF:
(COND B == 1
	(IOPATH A Y (0.062:0.062:0.062) (0.048:0.048:0.048)
	)
)
-- VHDL generic:
tpd_A_Y_B_EQ_1 : VitalDelayType01;

// Verilog HDL specify path:
if (B == 1'b1)
	(A *> Y) = (tplh$A$Y, tphl$A$Y);

• 从输入端口$CK$到输出端口$ECK$的传播延迟：

// SDF:
(IOPATH CK ECK (0.097:0.097:0.097))

-- VHDL generic:
tpd_CK_ECK : VitalDelayType01;

// Verilog HDL specify path:
(CK *> ECK) = (tplh$CK$ECK, tphl$CK$ECK);

• 从输入端口$CI$到输出端口$S$的条件传播延迟：

// SDF:
(COND (A == 0 && B == 0) || (A == 1 && B == 1)
	(IOPATH CI S (0.511) (0.389)
	)
)

-- VHDL generic:
tpd_CI_S_OP_A_EQ_0_AN_B_EQ_0_CP_OR_OP_A_EQ_1_AN_B_EQ_1_CP:
	VitalDelayType01;

// Verilog HDL specify path:
if ((A == 1'b0 && B == 1'b0) || (A == 1'b1 && B == 1'b1))
	(CI *> S) = (tplh$CI$S, tphl$CI$S);

• 从输入端口$CS$到输出端口$S$的条件传播延迟：

// SDF:
(COND (A == 1 ^ B == 1 ^ CI1 == 1) &&
		!(A == 1 ^ B == 1 ^ CI0 == 1)
	(IOPATH CS S (0.110) (0.120) (0.120)
	(0.110) (0.119) (0.120)
	)
)

-- VHDL generic:
tpd_CS_S_OP_A_EQ_1_XOB_B_EQ_1_XOB_CI1_EQ_1_CP_AN_NT_
OP_A_EQ_1_XOB_B_EQ_1_XOB_CI0_EQ_1_CP:
	VitalDelayType01;
	
// Verilog HDL specify path:
if ((A == 1'b1 ^ B == 1'b1 ^ CI1N == 1'b0) &&
		!(A == 1'b1 ^ B == 1'b1 ^ CI0N == 1'b0))
	(CS *> S) = (tplh$CS$S, tphl$CS$S);

• 从输入端口$A$到输出端口$ICO$的条件传播延迟：

// SDF:
(COND B == 1 (IOPATH A ICO (0.690)))

-- VHDL generic:
tpd_A_ICO_B_EQ_1 : VitalDelayType01;

// Verilog HDL specify path:
if (B == 1'b1)
	(A *> ICO) = (tplh$A$ICO, tphl$A$ICO);

• 从输入端口$A$到输出端口$CO$的条件传播延迟：

// SDF:
(COND (B == 1 ^ C == 1) && (D == 1 ^ ICI == 1)
	(IOPATH A CO (0.263)
	)
)

-- VHDL generic:
tpd_A_CO_OP_B_EQ_1_XOB_C_EQ_1_CP_AN_OP_D_EQ_1_XOB_ICI_E
Q_1_CP: VitalDelayType01;

// Verilog HDL specify path:
if ((B == 1'b1 ^ C == 1'b1) && (D == 1'b1 ^ ICI == 1'b1))
	(A *> CO) = (tplh$A$CO, tphl$A$CO);

• 从$CK$的上升沿到$Q$的延迟：

// SDF:
(IOPATH (posedge CK) Q (0.410:0.410:0.410)
(0.290:0.290:0.290))

-- VHDL generic:
tpd_CK_Q_posedge_noedge : VitalDelayType01;

// Verilog HDL specify path:
(posedge CK *> Q) = (tplh$CK$Q, tphl$CK$Q);

---

输入建立时间(Input Setup Time)

• $D$的上升沿与$CK$的上升沿之间的建立时间：

// SDF:
(SETUP (posedge D) (posedge CK) (0.157:0.157:0.157))

-- VHDL generic:
tsetup_D_CK_posedge_posedge: VitalDelayType;

// Verilog HDL timing check task:
$setup(posedge CK, posedge D, tsetup$D$CK, notifier);

• $D$的下降沿与$CK$的上升沿之间的建立时间：

// SDF:
(SETUP (negedge D) (posedge CK) (0.240))

-- VHDL generic:
tsetup_D_CK_negedge_posedge: VitalDelayType;

// Verilog HDL timing check task:
$setup(posedge CK, negedge D, tsetup$D$CK, notifier);

• 输入端口$E$的上升沿与参考$CK$的上升沿之间的建立时间：

// SDF:
(SETUP (posedge E) (posedge CK) (-0.043:-0.043:-0.043))

-- VHDL generic:
tsetup_E_CK_posedge_posedge : VitalDelayType;

// Verilog HDL timing check task:
$setup(posedge CK, posedge E, tsetup$E$CK, notifier);

• 输入端口$E$的下降沿和参考$CK$的上升沿之间的建立时间：

// SDF:
(SETUP (negedge E) (posedge CK) (0.101) (0.098))

-- VHDL generic:
tsetup_E_CK_negedge_posedge : VitalDelayType;

// Verilog HDL timing check task:
$setup(posedge CK, negedge E, tsetup$E$CK, notifier);

• $SE$和$CK$之间的条件建立时间：

// SDF:
(SETUP (cond E != 1 SE) (posedge CK) (0.155) (0.135))

-- VHDL generic:
tsetup_SE_CK_E_NE_1_noedge_posedge : VitalDelayType;

// Verilog HDL timing check task:
$setup(posedge CK &&& (E != 1'b1), SE, tsetup$SE$CK,
	notifier);

---

输入保持时间(Input Hold Time)

• $D$的上升沿与$CK$的上升沿之间的保持时间：

// SDF:
(HOLD (posedge D) (posedge CK) (-0.166:-0.166:-0.166))

-- VHDL generic:
thold_D_CK_posedge_posedge: VitalDelayType;

// Verilog HDL timing check task:
$hold (posedge CK, posedge D, thold$D$CK, notifier);

• $RN$与$SN$之间的保持时间：

// SDF:
(HOLD (posedge RN) (posedge SN) (-0.261:-0.261:-0.261))

-- VHDL generic:
thold_RN_SN_posedge_posedge: VitalDelayType;

// Verilog HDL timing check task:
$hold (posedge SN, posedge RN, thold$RN$SN, notifier);

• 输入端口$SI$与参考端口$CK$之间的保持时间：

// SDF:
(HOLD (negedge SI) (posedge CK) (-0.110:-0.110:-0.110))

-- VHDL generic:
thold_SI_CK_negedge_posedge: VitalDelayType;

// Verilog HDL timing check task:
$hold (posedge CK, negedge SI, thold$SI$CK, notifier);

• $E$和$CK$上升沿之间的条件保持时间：

// SDF:
(HOLD (COND SE ^ RN == 0 E) (posedge CK))

-- VHDL generic:
thold_E_CK_SE_XOB_RN_EQ_0_noedge_posedge:
	VitalDelayType;

// Verilog HDL timing check task:
$hold (posedge CK &&& (SE ^ RN == 0), posedge E,
thold$E$CK, NOTIFIER);

---

输入建立和保持时间(Input Setup and Hold Time)

• 在$D$和$CLK$之间的建立时间与保持时间检查。这是一个有条件的检查，第一个延迟值是建立时间，第二个延迟值是保持时间：

// SDF:
(SETUPHOLD (COND SE ^ RN == 0 D) (posedge CLK)
	(0.69) (0.32))
	
-- VHDL generic (split up into separate setup and hold):
tsetup_D_CK_SE_XOB_RN_EQ_0_noedge_posedge:
	VitalDelayType;
thold_D_CK_SE_XOB_RN_EQ_0_noedge_posedge:
	VitalDelayType;
	
-- Verilog HDL timing check (it can either be split up or
-- kept as one construct depending on what appears in the
-- Verilog HDL model):
$setuphold(posedge CK &&& (SE ^ RN == 1'b0)), posedge D,
		tsetup$D$CK, thold$D$CK, notifier);
-- Or as:

---

输入恢复时间(Input Recovery Time)

• $CLKA$和$CLKB$之间的恢复时间：

// SDF:
(RECOVERY (posedge CLKA) (posedge CLKB)
	(1.119:1.119:1.119))
	
-- VHDL generic:
trecovery_CLKA_CLKB_posedge_posedge: VitalDelayType;

// Verilog timing check task:
$recovery (posedge CLKB, posedge CLKA,
		trecovery$CLKB$CLKA, notifier);

• $CLKA$上升沿与$CLKB$上升沿之间的条件恢复时间：

// SDF:
(RECOVERY (posedge CLKB)
	(COND ENCLKBCLKArec (posedge CLKA)) (0.55:0.55:0.55)
)

-- VHDL generic:
trecovery_CLKB_CLKA_ENCLKBCLKArec_EQ_1_posedge_
posedge: VitalDelayType;

// Verilog timing check task:
$recovery (posedge CLKA && ENCLKBCLKArec, posedge CLKB,
		trecovery$CLKA$CLKB, notifier);

• $SE$与$CK$之间的恢复时间：

// SDF:
(RECOVERY SE (posedge CK) (1.901))

-- VHDL generic:
trecovery_SE_CK_noedge_posedge: VitalDelayType;

// Verilog timing check task:
$recovery (posedge CK, SE, trecovery$SE$CK, notifier);

• $RN$与$CK$之间的恢复时间：

// SDF:
(RECOVERY (COND D == 0 (posedge RN)) (posedge CK) (0.8))

-- VHDL generic:
trecovery_RN_CK_D_EQ_0_posedge_posedge:
	VitalDelayType;
	
// Verilog timing check task:
$recovery (posedge CK && (D == 0), posedge RN,
		trecovery$RN$CK, notifier);

---

输入撤销时间(Input Removal Time)

• $E$的上升沿与$CK$的下降沿之间的撤销时间：

// SDF:
(REMOVAL (posedge E) (negedge CK) (0.4:0.4:0.4))

-- VHDL generic:
tremoval_E_CK_posedge_negedge: VitalDelayType;

// Verilog timing check task:
$removal (negedge CK, posedge E, tremoval$E$CK,
		notifier)

• $CK$的上升沿和$SN$之间的条件撤销时间：

// SDF:
(REMOVAL (COND D != 1'b1 SN) (posedge CK) (1.512))

-- VHDL generic:
tremoval_SN_CK_D_NE_1_noedge_posedge : VitalDelayType;

// Verilog timing check task:
$removal (posedge CK &&& (D != 1'b1), SN,
		tremoval$SN$CK, notifier);

---

周期(Period)

• 输入$CLKB$的周期：

// SDF:
(PERIOD CLKB (0.803:0.803:0.803))

-- VHDL generic:
tperiod_CLKB: VitalDelayType;

// Verilog timing check task:
$period (CLKB, tperiod$CLKB);

• 输入端口$EN$的周期：

// SDF:
(PERIOD EN (1.002:1.002:1.002))

-- VHDL generic:
tperiod_EN : VitalDelayType;

// Verilog timing check task:
$period (EN, tperiod$EN);

• 输入端口$TCK$的周期：

// SDF:
(PERIOD (posedge TCK) (0.220))

-- VHDL generic:
tperiod_TCK_posedge: VitalDelayType;

// Verilog timing check task:
$period (posedge TCK, tperiod$TCK);

---

脉宽(Pulse Width)

• $CK$上高脉冲的脉冲宽度：

// SDF:
(WIDTH (posedge CK) (0.103:0.103:0.103))

-- VHDL generic:
tpw_CK_posedge: VitalDelayType;

// Verilog timing check task:
$width (posedge CK, tminpwh$CK, 0, notifier);

• $CK$上低脉冲的脉冲宽度：

// SDF:
(WIDTH (negedge CK) (0.113:0.113:0.113)

-- VHDL generic:
tpw_CK_negedge: VitalDelayType;

// Verilog timing check task:
$width (negedge CK, tminpwl$CK, 0, notifier);

• $RN$上高脉冲的脉冲宽度：

// SDF:
(WIDTH (posedge RN) (0.122))

-- VHDL generic:
tpw_RN_posedge: VitalDelayType;

// Verilog timing check task:
$width (posedge RN, tminpwh$RN, 0, notifier);

---

输入偏斜时间(Input Skew Time)

• $CK$与$TCK$之间的偏斜：

// SDF:
(SKEW (negedge CK) (posedge TCK) (0.121))

-- VHDL generic:
tskew_CK_TCK_negedge_posedge: VitalDelayType;

// Verilog timing check task:
$skew (posedge TCK, negedge CK, tskew$TCK$CK, notifier);

• $SE$和$CK$下降沿之间的偏斜：

// SDF:
(SKEW SE (negedge CK) (0.386:0.386:0.386))

-- VHDL generic:
tskew_SE_CK_noedge_negedge: VitalDelayType;

// Verilog HDL timing check task:
$skew (negedge CK, SE, tskew$SE$CK, notifier);

---

无变化的建立时间(No-change Setup Time)

$SDF$文件中的NOCHANGE结构将同时映射到$VHDL$中的tncsetup和tnchold泛型。

• $D$和$CK$下降沿之间无变化的建立时间：

// SDF:
(NOCHANGE D (negedge CK) (0.343:0.343:0.343))

-- VHDL generic:
tncsetup_D_CK_noedge_negedge: VitalDelayType;
tnchold_D_CK_noedge_negedge: VitalDelayType;

// Verilog HDL timing check task:
$nochange (negedge CK, D, tnochange$D$CK, notifier);

---

无变化的保持时间(No-change Hold Time)

$SDF$文件中的NOCHANGE结构将同时映射到$VHDL$中的tncsetup和tnchold泛型。

• $E$和$CLKA$之间无变化的条件保持时间：

// SDF:
(NOCHANGE (COND RST == 1'b1 (posedge E)) (posedge CLKA)
(0.312))

-- VHDL generic:
tnchold_E_CLKA_RST_EQ_1_posedge_posedge:
	VitalDelayType;
tncsetup_E_CLKA_RST_EQ_1_posedge_posedge:
	VitalDelayType;

// Verilog HDL timing check task:
$nochange (posedge CLKA &&& (RST == 1'b1), posedge E,
		tnochange$E$CLKA, notifier);

---

端口延迟(Port Delay)

• 端口$OE$的延迟：

// SDF:
(PORT OE (0.266))

-- VHDL generic:
tipd_OE: VitalDelayType01;

// Verilog HDL:
No explicit Verilog declaration.

• 端口$RN$的延迟：

// SDF:
(PORT RN (0.201:0.205:0.209))

-- VHDL generic:
tipd_RN : VitalDelayType01;

// Verilog HDL:
No explicit Verilog declaration.

---

网络延迟(Net Delay)

• 连接到端口$CKA$的网络延迟：

// SDF:
(NETDELAY CKA (0.134))

-- VHDL generic:
tipd_CKA: VitalDelayType01;

// Verilog HDL:
No explicit Verilog declaration.

---

互连路径延迟(Interconnect Path Delay)

• 从端口$Y$到端口$D$的互连路径延迟：

// SDF:
(INTERCONNECT bcm/credit_manager/U304/Y
	bcm/credit_manager/frame_in/PORT0_DOUT_Q_reg_26_/D
	(0.002:0.002:0.002) (0.002:0.002:0.002))

-- VHDL generic of instance
-- bcm/credit_manager/frame_in/PORT0_DOUT_Q_reg_26_:
tipd_D: VitalDelayType01;
-- The “from” port does not contribute to the timing
-- generic name.

// Verilog HDL:
No explicit Verilog declaration

---

器件延迟(Device Delay)

• 实例$uP$的输出$SM$的器件延迟：

// SDF:
(INSTANCE uP) . . . (DEVICE SM . . .

-- VHDL generic:
tdevice_uP_SM

// Verilog specify paths:
// All specify paths to output SM.

---

---

B.5 完整语法(Complete Syntax)

以下是使用$BNF$格式显示的$SDF$的完整语法。终端（terminal）名称是大写的，关键字是粗体的，但是不区分大小写。起始的终端是delay_file：

---

---

知乎翻译圣经

静态时序分析圣经翻译计划——附录B：SDF （下）