SystemVerilog 中一些数据类型

最新推荐文章于 2022-04-29 16:11:26 发布

yuexiangallan

最新推荐文章于 2022-04-29 16:11:26 发布

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分类专栏： systemverilog 文章标签： systemverilog

本文链接：https://blog.csdn.net/yuexiangallan/article/details/121691332

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本文介绍了SystemVerilog中的数据类型，包括packed array（向量细分）、unpacked array（分别处理元素）、内存（reg、logic或bit的一维数组）以及多维数组（MDA）的概念。此外，还提到了动态数组，这种类型的尺寸可以在运行时设置或更改。

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packed array:

An array where the dimensions are declared before an object name. Packed arrays can have any number of dimensions. A one-dimensional packed array is the same as a vector width declaration in IEEE 1364-2005 Verilog. Packed arrays provide a mechanism for subdividing a vector into subfields, which can be conveniently accessed as array elements. A packed array differs from an unpacked array, in that the whole array is treated as a single vector for arithmetic operations.

For example:

bit [7:0] a; // packed array of scalar bit types

unpacked array:

An array where the dimensions are declared after an object name. Unpacked arrays are the same as arrays in IEEE 1364-2005 Verilog and can have any number of dimensions. An unpacked array differs from a packed array in that the whole array cannot be used for arithmetic operations. Each element shall be treated separately.

For example: