2021-06-11实验

一、实验要求：用Modlsim进行ModelSim软件的仿真
二.Modelsim的工程仿真流程图如下:

无

三、实验内容：
参考老师发的视频的代码，然后用Modelsim进行Modelsim的工程仿真

四、实验原理代码图:
1、仿真代码

五、实验工具：Modlsim软件、pc机。
六、实验截图：
7-1

7_3

8-1

七、实验视频:

7-1,7-3,8-1

八、实验代码:

7-1
module my_rs (reset,set,q, qbar);
input reset,set;
output q, qbar;
nor #(1) n1 (q, reset, qbar);
nor #(1) n2 (qbar,set,q) ;
endmodule
7-3
module div2(clk, reset, start, A, B, D, R, ok, err);
parameter n = 32;
parameter m = 16;

input clk, reset, start;
input [n-1:0] A, B;
output [n+m-1:0] D;
output [n-1:0] R;
output ok, err;

wire invalid, carry, load, run;

div_ctl UCTL(clk, reset, start, invalid, carry, load, run, err, ok);
div_datapath UDATAPATH(clk, reset, A, B, load, run, invalid, carry, D, R);

endmodule

module div_ctl(clk, reset, start, invalid, carry, load, run, err, ok);
parameter n = 32;
parameter m = 16;
parameter STATE_INIT = 3’b001;
parameter STATE_RUN = 3’b010;
parameter STATE_FINISH = 3’b100;
input clk, reset, start, invalid, carry;
output load, run, err, ok;

reg [2:0] current_state, next_state;
reg [5:0] cnt;
reg load, run, err, ok;

always @(posedge clk or negedge reset)
begin
if(!reset) begin
current_state <= STATE_INIT;
cnt <= 0;
end else begin
current_state <= next_state;
if(run) cnt <= cnt + 1’b1;
end
end

always @(posedge clk or negedge reset)
begin
if(!reset) begin
err <= 0;
end else if(next_state==STATE_RUN) begin
if(invalid) err <= 1;
end
end

always @(current_state or start or invalid or carry or cnt)

begin
load <= 1’b0;
ok <= 1’b0;
run <= 1’b0;

  case(current_state)
     STATE_INIT: begin
        if(start) next_state <= STATE_RUN;
        else next_state <= STATE_INIT;
        load <= 1;
     end
     STATE_RUN : begin
        run <= 1;
        if(invalid) begin
           next_state <= STATE_FINISH;   
        end else if(cnt==(n+m-1)) begin
           next_state <= STATE_FINISH;    
        end else begin
           next_state <= STATE_RUN;
        end
     end
     STATE_FINISH : begin
        ok <= 1;
        next_state <= STATE_FINISH;    
     end
     default : begin
        next_state <= STATE_INIT;    
     end
  endcase

end
endmodule

module div_datapath(clk, reset, A, B, load, run, invalid, carry, D, R);
parameter n = 32;
parameter m = 16;
input clk, reset;
input [n-1:0] A, B;
input load, run;
output invalid, carry;
output [n+m-1:0] D;
output [n-1:0] R;

reg [n+n+m-2:0] R0;
reg [n+m-1:0] D;
reg [n-1:0] B0;
reg carry;

wire invalid;
wire [n-1:0] DIFF, R;
wire CO;

assign R = {carry, R0[n+n+m-2:n+m]};
assign invalid = (B0==0);

sub sub(R0[n+n+m-2:n+m-1], B0, 1’b0, DIFF, CO); //ʵÀý»¯¼õ·¨Æ÷

always @(posedge clk)
begin
if(load) begin //³õʼ½×¶Î
D <= 0;
R0 <= {{(n-1){1’b0}}, A, {m{1’b0}}};
B0 <= B;
carry <= 1’b0;
end
else if(run) begin //½áÊø½×¶Î
if(CO && !carry) begin
R0 <= { R0, 1’b0 };
D <= { D[n+m-2:0], 1’b0 };
carry <= R0[n+n+m-2];
end else begin //µü´ú½×¶Î
R0 <= { DIFF, R0[n+m-2:0], 1’b0 };
D <= { D[n+m-2:0], 1’b1 };
carry <= DIFF[n-1];
end
end
end
endmodule

module sub(A, B, CI, DIFF, CO);
parameter n = 32;
input [n-1:0] A, B;
input CI;
output [n-1:0] DIFF;
output CO;

assign {CO, DIFF} = {1’b0, A} - {1’b0, B} - {{n{1’b0}}, CI};
endmodule
8-3
module ex8_1(clock,reset,x,y1,y2) ;
input clock,reset;
input x;
output y1,y2;
reg y1,y2;

reg [3:0] cstate,nstate;

parameter s0=4’b0001,s1=4’b0010,
s2=4’b0100,s3=4’b1000;

always @ (posedge clock or posedge reset)
begin
if (reset)
cstate<=s0;
else
cstate<=nstate;
end

always @ (cstate or x)
begin
case (cstate)
s0:begin
if (x0)
nstate=s1;
else
nstate=s3;
end
s1:begin
if (x0)
nstate=s2;
else
nstate=s0;
end
s2:begin
if (x0)
nstate=s3;
else
nstate=s1;
end
s3:begin
if (x0)
nstate=s0;
else
nstate=s2;
end
default : nstate=s0;
endcase
end

always @ (cstate or x)
begin
case (cstate)
s0 : begin
if (x0)
y1=1;
else
y1=0;
end
s1 : begin
if (x0)
y1=0;
else
y1=0;
end
s2 : begin
if (x0)
y1=0;
else
y1=0;
end
s3 : begin
if (x0)
y1=0;
else
y1=1;
end
default :y1=0;
endcase
end

always @ (cstate or x)
begin
if (cstates0 && x0)
y2=1;
else if (cstates3 && x1)
y2=1;
else
y2=0;
end