学习日志之computer architecture(3)

最新推荐文章于 2022-09-22 19:07:26 发布

Akimoto Akira

最新推荐文章于 2022-09-22 19:07:26 发布

阅读量345

点赞数

分类专栏： MIPS pipeline

本文链接：https://blog.csdn.net/zch951127/article/details/104404623

版权

MIPS pipeline 专栏收录该内容

4 篇文章 0 订阅

订阅专栏

speculation based on hw

multiple issue processor

(m,n)correlating prediction

branch-target buffer

misunderstanding about data hazard

speculation based on hw

speculation is aiming to solve the particular problem happen in the architecture based on Tomasulo algorithm. it's a technique for reducing the effects of control dependences in a processor implementing.

the main idea of this method is to add a reorder buffer between CDB and FP register. This buffer can provide data directly to the reservation station. the main function of this buffer is to allow data committed in order in the commit stage rather than write result stage. and only if the processor commits the result, it can be written to the register.

the following table shows the difference between the previous version of Tomasulo scheduling

multiple issue processor

the main idea of this method is to increase the thread of issuing instructions to reduce the clock cycle used by each instruction. in this way, the clock cycle used by instruction can be even less than 1 clock cycle. and the processor can commit two or even more results at the same time. (commit stage should be later than write result stage)

(m,n)correlating prediction

this method means that use the previous m branches' results to predict the result of the current branch result. They use the behavior of the last m branches to choose from 2m branch predictors, each of which is a n-bit predictor

e.g. (2,2) predictor implementation