github上点赞前100的关于UVM的仓库

NAME	OWNER	STARS	URL	DESCRIPTION
uvmprimer	raysalemi	174	https://github.com/raysalemi/uvmprimer	Contains the code examples from The UVM Primer Book sorted by chapters.
logic	tymonx	136	https://github.com/tymonx/logic	CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
UVMReference	VerificationExcellence	110	https://github.com/VerificationExcellence/UVMReference	Reference examples and short projects using UVM Methodology
uvm-tutorial-for-candy-lovers	cluelogic	79	https://github.com/cluelogic/uvm-tutorial-for-candy-lovers	Source code repo for UVM Tutorial for Candy Lovers
svaunit	amiq-consulting	49	https://github.com/amiq-consulting/svaunit	SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
tvip-axi	taichi-ishitani	47	https://github.com/taichi-ishitani/tvip-axi	AMBA AXI VIP
AHB2	GodelMachine	43	https://github.com/GodelMachine/AHB2	AMBA AHB 2.0 VIP in SystemVerilog UVM
uvm_agents	dovstamler	41	https://github.com/dovstamler/uvm_agents	UVM agents
UVM	mayurkubavat	38	https://github.com/mayurkubavat/UVM	UVM examples and projects
tnoc	taichi-ishitani	37	https://github.com/taichi-ishitani/tnoc	Network on Chip Implementation written in SytemVerilog
combinator-uvm	doswellf	27	https://github.com/doswellf/combinator-uvm	UVM Testbench For SystemVerilog Combinator Implementation
axi-uvm	marcoz001	23	https://github.com/marcoz001/axi-uvm	yet another AXI testbench repo. 😉 This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
custom_uvm_report_server	kaushalmodi	18	https://github.com/kaushalmodi/custom_uvm_report_server	Customized UVM Report Server
uvm-utest	nosnhojn	17	https://github.com/nosnhojn/uvm-utest	None
AMBA_APB_SRAM	courageheart	16	https://github.com/courageheart/AMBA_APB_SRAM	AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
ISP_UVM	nelsoncsc	15	https://github.com/nelsoncsc/ISP_UVM	A Framework for Design and Verification of Image Processing Applications using UVM
second_edition	advanced-uvm	15	https://github.com/advanced-uvm/second_edition	Code for the second edition of Advanced UVM.
uvm_debug	uvmdebug	13	https://github.com/uvmdebug/uvm_debug	UVM interactive debug library
easyUVM	nelsoncsc	13	https://github.com/nelsoncsc/easyUVM	A simple UVM example with DPI
UVM	chiggs	12	https://github.com/chiggs/UVM	Mirror of the Universal Verification Methodology from sourceforge
uvm_apb	smartfoxdata	12	https://github.com/smartfoxdata/uvm_apb	uvm_apb is a uvm package for modeling and verifying APB (Advanced Periperal Bus) protocol
uvm_gen	hjking	11	https://github.com/hjking/uvm_gen	UVM Generator
uvm-components	pulp-platform	11	https://github.com/pulp-platform/uvm-components	Contains commonly used UVM components (agents, environments and tests).
uvm_candy_lover	zhajio1988	10	https://github.com/zhajio1988/uvm_candy_lover	🍬UVM candy lover testbench which uses YASA as simulation script
ref-uvm-i2c-wb	ic7x24	10	https://github.com/ic7x24/ref-uvm-i2c-wb	None
jarvisuk	shady831213	9	https://github.com/shady831213/jarvisuk	Just A Really Very Impressive Systemverilog UVM Kit
freecellera-uvm	Freecellera	8	https://github.com/Freecellera/freecellera-uvm	Freecellera fork of the Universal Verification Methodology (SystemVerilog verification library from Accellera.org)
RISC_VERIF_DEMO_0	MushroomZQ	8	https://github.com/MushroomZQ/RISC_VERIF_DEMO_0	a very simple risc_cpu verification demo with uvm
uvm_reg_to_ipxact	amiq-consulting	8	https://github.com/amiq-consulting/uvm_reg_to_ipxact	None
uvm_axi	smartfoxdata	8	https://github.com/smartfoxdata/uvm_axi	uvm_axi is a uvm package for modeling and verifying AXI protocol
uvm_axi4lite	smartfoxdata	8	https://github.com/smartfoxdata/uvm_axi4lite	uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
uvm	accellera	7	https://github.com/accellera/uvm	None
ahb3_uvm_tb	designsolver	7	https://github.com/designsolver/ahb3_uvm_tb	AMBA 3 AHB UVM TB
yuu_ahb	seabeam	7	https://github.com/seabeam/yuu_ahb	UVM AHB VIP
uvm_starter	smartfoxdata	7	https://github.com/smartfoxdata/uvm_starter	uvm_starter is a simple template for starting uvm projects
YasaUvk	zhajio1988	7	https://github.com/zhajio1988/YasaUvk	🐛UVM verification kits which uses YASA as simulation script
AHB-APB_Bridge_UVM_Env	Gateway91	6	https://github.com/Gateway91/AHB-APB_Bridge_UVM_Env	AHB-APB UVM Verification Environment
UVM-APB_RAL	JoseIuri	5	https://github.com/JoseIuri/UVM-APB_RAL	This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
yamm	amiq-consulting	5	https://github.com/amiq-consulting/yamm	YAMM package repository
Gaia	GeraltShi	5	https://github.com/GeraltShi/Gaia	Generate UVM testbench framework template files with Python 3
gpio_agent	imokanj	5	https://github.com/imokanj/gpio_agent	General Purpose I/O agent written in UVM
UART	darthsider	5	https://github.com/darthsider/UART	UART design in SV and verification using UVM and SV
uvm_sin_cos_table	vlotnik	5	https://github.com/vlotnik/uvm_sin_cos_table	Contains source code for sin/cos table verification using UVM
UVM-Verification-Testbench-For-SimpleBus	rdou	5	https://github.com/rdou/UVM-Verification-Testbench-For-SimpleBus	None
yuu_apb	seabeam	5	https://github.com/seabeam/yuu_apb	UVM APB VIP, part of AMBA3&AMBA4 feature supported
regModel	briandong	5	https://github.com/briandong/regModel	This script builds the UVM register model, based on pre-defined address map in markdown (mk) style
sva_traces	go2uvm	5	https://github.com/go2uvm/sva_traces	Traces for SVA - SystemVerilog Assertions; Will use Go2UVM package to write traces and use uvm_report_mock to predict errors
uvm_agent_gen	blargony	4	https://github.com/blargony/uvm_agent_gen	UVM Agent Generator
i2c_wb_sv_uvm	rajkumarraval	4	https://github.com/rajkumarraval/i2c_wb_sv_uvm	None
UVM-Simulation-JTAG	serinvarghese	4	https://github.com/serinvarghese/UVM-Simulation-JTAG	UVM Simulation Model for a JTAG Interface
UvmEnvUartApb	nguyenquanicd	4	https://github.com/nguyenquanicd/UvmEnvUartApb	This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetigating the UVM env.
tue	taichi-ishitani	4	https://github.com/taichi-ishitani/tue	Useful UVM extensions
uvmgen	edcote	4	https://github.com/edcote/uvmgen	UVM verification component and testbench generator tool
cagt	amiq-consulting	4	https://github.com/amiq-consulting/cagt	Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast an UVM based agent for any protocol.
UVM_Verification	avashist003	4	https://github.com/avashist003/UVM_Verification	Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
tvip-apb	taichi-ishitani	4	https://github.com/taichi-ishitani/tvip-apb	Verification IP for AMBA APB Protocol
uvm_auto	mingzhang952	3	https://github.com/mingzhang952/uvm_auto	uvm auto generator
uart2bustestbench	hanysalah	3	https://github.com/hanysalah/uart2bustestbench	UVM Verification IP to uart2bus IP.
uvm-phase-jumping	PedroHSCavalcante	3	https://github.com/PedroHSCavalcante/uvm-phase-jumping	Simple UVM phase jumping
UVM-Verification-Testbench-For-FIFO	rdou	3	https://github.com/rdou/UVM-Verification-Testbench-For-FIFO	A complete UVM verification testbench for FIFO
uvm	kippy620	3	https://github.com/kippy620/uvm	Learning uvm step by step.
Async_FIFO_Verification	akzare	3	https://github.com/akzare/Async_FIFO_Verification	Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
uvmBasics	adibis	3	https://github.com/adibis/uvmBasics	Basics of UVM via an APB slave
yuu_vip_gen	seabeam	3	https://github.com/seabeam/yuu_vip_gen	UVM VIP architecture generator
UVM_primer	hmomkar	3	https://github.com/hmomkar/UVM_primer	Contains UVM example from Ray salemi authored book
sv_practice	harpreetbhatia	3	https://github.com/harpreetbhatia/sv_practice	Practice exercises for SystemVerilog, UVM …
RISCV-UVM-Verification	vatsal184	3	https://github.com/vatsal184/RISCV-UVM-Verification	None
A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM	alice820621	3	https://github.com/alice820621/A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM	A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence generates addresses and allows the driver to tell the BFM which slave to choose. Subsequently four monitors and scoreboards record each slave’s test results.
async_FIFO	dadongshangu	3	https://github.com/dadongshangu/async_FIFO	This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming’s paper and the UVM is coded by me(Xianghzi Meng)
wishbone_uvc	alexzhang007	3	https://github.com/alexzhang007/wishbone_uvc	Wishbone protocol open source universal verification component (UVC). It is easy to be used in UVM verification environment for opencpu.
yuu_clock	seabeam	3	https://github.com/seabeam/yuu_clock	UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available
uvm	aravindprakash	2	https://github.com/aravindprakash/uvm	UVM Examples
uvm	SymbiFlow	2	https://github.com/SymbiFlow/uvm	None
UVM_Python_UVMC	JoseIuri	2	https://github.com/JoseIuri/UVM_Python_UVMC	This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor®.
MAC_BFM	jchengX	2	https://github.com/jchengX/MAC_BFM	wifi
uvm_lab	chenfengrugao	2	https://github.com/chenfengrugao/uvm_lab	a pratical uvm lab
uvm_testbench	mowsong	2	https://github.com/mowsong/uvm_testbench	SoC Verification with UVM
UVM_UART_Example	WeiChungWu	2	https://github.com/WeiChungWu/UVM_UART_Example	An UVM example of UART
apb_uvm	chan-henry	2	https://github.com/chan-henry/apb_uvm	Advanced Peripheral Bus (APB) UVM testbench project
uvm-templates	nbrummel	2	https://github.com/nbrummel/uvm-templates	This repo provides uvm templates to start a sv uvm project.
UVM_verification	ganesh-ps	2	https://github.com/ganesh-ps/UVM_verification	None
SimpleAdder-UVM	tamannarupani	2	https://github.com/tamannarupani/SimpleAdder-UVM	A simple adder implementation and verification using UVM 1.2
uvm-indirect-registers	uwesimm	2	https://github.com/uwesimm/uvm-indirect-registers	an infrastructure to implement arbitrary indirect registers on top of uvm
ExtremeDV_UVM	zhajio1988	2	https://github.com/zhajio1988/ExtremeDV_UVM	UVM resource from github, run simulation use YASAsim flow
MPSoC-DV	PacoReinaCampo	2	https://github.com/PacoReinaCampo/MPSoC-DV	MPSoC verified with UVM/OSVVM/FV
cpu	kruegz	2	https://github.com/kruegz/cpu	CPU design with SystemVerilog/UVM verification
UVM-Verification-Testbench-For-APB	rdou	2	https://github.com/rdou/UVM-Verification-Testbench-For-APB	None
UVM-Testbench-for-Flex-Timer	hrishikeshpujari	2	https://github.com/hrishikeshpujari/UVM-Testbench-for-Flex-Timer	None
UART-16550	Shivanagender123	2	https://github.com/Shivanagender123/UART-16550	This is UVM testbench for UART with multiple test cases.
SoC-DV	PacoReinaCampo	2	https://github.com/PacoReinaCampo/SoC-DV	System on Chip verified with UVM/OSVVM/FV
AHB_APB-Bridge	Shivanagender123	2	https://github.com/Shivanagender123/AHB_APB-Bridge	This is normal basic UVM testbench for AMBA Bridge AHB_APB
Shift_Register	Shivanagender123	2	https://github.com/Shivanagender123/Shift_Register	This is normal basic UVM testbench for shift register with reference model using queues in scoreboard and RTL
uvm	akilystic	1	https://github.com/akilystic/uvm	None
UVM	tyxuanyuanlx	1	https://github.com/tyxuanyuanlx/UVM	None
AHB-with-FIFO	Emi-Pushpam	1	https://github.com/Emi-Pushpam/AHB-with-FIFO	UVM methodology
basic_uvmc_oct	nelsoncsc	1	https://github.com/nelsoncsc/basic_uvmc_oct	A simple UVM testbench using UVM Connect and Octave
uvm_ahb_lite	zhelnio	1	https://github.com/zhelnio/uvm_ahb_lite	uvm ahb lite environment
SMC_Verification	fifthheaven	1	https://github.com/fifthheaven/SMC_Verification	verify SMC via UVM
uvm_objections	dcblack	1	https://github.com/dcblack/uvm_objections	UVM Objection performance
uvm_uart_apb_env	nguyensinhton9x	1	https://github.com/nguyensinhton9x/uvm_uart_apb_env	uvm_ver_3